NXP Semiconductors LPC2917, LPC2919 user manual PLL functional description

NXP Semiconductors

DRAFT	D	D		AFT
	RAFT	RAFT AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T DRAFT	T
DRA	DRA	DR
F	F
and values of ’CLK_SEL’ that would select those clocks are masked and notDRAFTwrittenDRAFTto the		DRAF
Clock Activity Detection: Clocks that are inactive are automatically regarded as invalid,

control registers. This is accomplished by adding a clock detector to every clock DRAFT DRAFT generator. The RDET register keeps track of which clocks are active and inactive, and the

appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock	DRAFT	D
detector can also generate interrupts at clock activation and deactivation so that the
system can be notified of a change in internal clock status.	DRA

Clock detection is done using a counter running at the BASE_PCR_CLK frequency. If no positive clock edge occurs before the counter has 32 cycles of BASE_PCR_CLK the clock is assumed to be inactive. As BASE_PCR_CLK is slower than any of the clocks to be detected, normally only one BASE_PCR_CLK cycle is needed to detect activity. After reset all clocks are assumed to be ‘non-present’, so the RDET status register will be correct only after 32 BASE_PCR_CLK cycles.

Note that this mechanism cannot protect against a currently-selected clock going from active to inactive state. Therefore an inactive clock may still be sent to the system under special circumstances, although an interrupt can still be generated to notify the system.

Glitch-Free Switching: Provisions are included in the CGU to allow clocks to be switched glitch-free, both at the output generator stage and also at secondary source generators.

In the case of the PLL the clock will be stopped and held low for long enough to allow the PLL to stabilize and lock before being re-enabled. For all non-PLL Generators the switch will occur as quickly as possible, although there will always be a period when the clock is held low due to synchronization requirements.

If the current clock is high and does not go low within 32 cycles of BASE_PCR_CLK it is assumed to be inactive and is asynchronously forced low. This prevents deadlocks on the interface.

8.8.4.3PLL functional description

A block diagram of the PLL is shown in Figure 14. The input clock is fed directly to the analog section. This block compares the phase and frequency of the inputs and generates the main clock2. These clocks are either divided by 2*P by the programmable post divider to create the output clock, or sent directly to the output. The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock. The output signal of the analog section is also monitored by the lock detector to signal when the PLL has locked onto the input clock.

2.Generation of the main clock is restricted by the frequency range of the PLL clock input. See Table 31, Dynamic characteristics.

LPC2917_19_1 © NXP B.V. 2007. All rights reserved.

Preliminary data sheet Rev. 1.01 — 15 November 2007 45 of 68