NXP Semiconductors LPC2917 Clocking strategy, Ieee 1149.1 interface pins Jtag boundary-scan test

NXP Semiconductors

DRAFT	D	D		AFT
	RAFT	RAFT AFT
			DR	DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

				DRA	DRAFT	DRA					DR
				F				F
7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)				T					T
				DRAFT DRAFT DRAF
	The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also							DRAFT
	referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test
					DRAFT
	pins can be used to connect a debugger probe for the embedded ARM processor. Pin						DRAFT				D
	JTAGSEL selects between boundary-scan mode and debug mode. Table 5 shows the
	boundary- scan test pins.
										DRA
	Table 5.	IEEE 1149.1 boundary-scan test and debug interface
	Symbol		Description
	JTAGSEL		TAP controller select input. LOW level selects ARM debug mode and HIGH level
			selects boundary scan and flash programming; pulled up internally
	TRSTN		test reset input; pulled up internally (active LOW)
	TMS		test-mode select input; pulled up internally
	TDI		test data input, pulled up internally
	TDO		test data output
	TCK		test clock input

7.1.4Power supply pins description

Table 6 shows the power supply pins.

Table 6.	Power supplies
Symbol		Description
VDD(CORE)		digital core supply 1.8 V
VSS(CORE)		digital core ground (digital core, ADC 1)
VDD(IO)		I/O pins supply 3.3 V
VSS(IO)		I/O pins ground
VDD(OSC)		oscillator and PLL supply
VSS(OSC)		oscillator ground
VDD(A3V3)		ADC 3.3 V supply
VSS(PLL)		PLL ground

7.2Clocking strategy

7.2.1Clock architecture

The LPC2917/19 contains several different internal clock areas. Peripherals like Timers, SPI, UART, CAN and LIN have their own individual clock sources called Base Clocks. All base clocks are generated by the Clock Generator Unit (CGU). They may be unrelated in frequency and phase and can have different clock sources within the CGU.

The system clock for the CPU and AHB Multilayer Bus infrastructure has its own base clock. This means most peripherals are clocked independently from the system clock. See Figure 3 for an overview of the clock areas within the device.

Within each clock area there may be multiple branch clocks, which offers very flexible control for power-management purposes. All branch clocks are outputs of the Power Management Unit (PMU) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. See Section 8.8 for more details of clock and power control within the device.

LPC2917_19_1 © NXP B.V. 2007. All rights reserved.

Preliminary data sheet Rev. 1.01 — 15 November 2007 11 of 68