NXP Semiconductors

DRAFT

D

D

 

AFT

RAFT

RAFT AFT

 

 

 

DR

DR

DLPC2917/19

ARM9 microcontrollerRAFT withDRAFTCANDRAFTand LINDRAFT

T DRAFT

T

DRA

DRA

DR

F

F

than or equal to the system clock frequency. To meet this constraint or to selectDRAFTtheDRAFT

DRAF

The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower

 

desired lower sampling frequency the clock generation unit provides a programmableDRAFT DRAFT fractional system-clock divider dedicated to the ADC clock. Conversion rate is determined

by the ADC clock frequency divided by the number of resolution bits plus one. Accessing

 

D

ADC registers requires an enabled ADC clock, which is controllable via the clock

DRAFT

 

generation unit, see Section 8.8.4.

 

DRA

 

 

Each ADC has four start inputs. Note that start 0 and start 2 are captured in the system clock domain while start 1 and start 3 are captured in the ADC domain. The start inputs are connected at MSCSS level, see Section 8.7.2.1 for details.

CLK_ADCx_VPB

CLK_ADCx

(MSCSS SubSystem clock)

(ADC clock)

(upto 4.5 MHz)

 

VPB SubSystem

 

 

 

 

ADC domain

 

 

domain

 

 

 

 

 

 

 

 

 

 

 

 

 

 

update

 

 

 

 

 

 

ADC

Conversion data

ADC

 

 

 

 

 

 

 

3.3 V

 

Analog

VPB

control

control

 

Analog

Analog

inputs

&

 

&

 

system

Config data

 

to

ADC1: 8

bus

 

registers

mux

registers

Digital

ADC2: 8

 

 

 

 

 

 

 

 

 

 

 

convertor

 

 

ADC

 

IRQ

 

 

 

 

 

 

 

 

 

 

 

 

IRQ

 

 

 

 

 

 

 

 

Start 0

Start 2

Start 1

Start 3

Sync_out

 

 

 

 

 

 

 

 

 

001aad331 **

Fig 9. ADC block diagram

8.7.5.3ADC pin description

The two ADC modules in the MSCSS have the pins described below. The ADCx input pins are combined with other functions on the port pins of the LPC2917/19. The VREFN and VREFP pins are common for both ADCs. Table 20 shows the ADC pins.

Table 20. Analog to digital converter pins

 

Symbol

Direction

Description

 

ADCn IN[7:0]

in

analog input for ADCn, channel 7 to channel 0 (n is 1 or 2)

 

 

 

 

ADCn_EXT_START in

ADC external start-trigger input (n is 1 or 2)

 

 

 

 

 

VREFN

in

ADC LOW reference level

 

 

 

 

 

VREFP

in

ADC HIGH reference level

 

 

 

 

LPC2917_19_1

 

© NXP B.V. 2007. All rights reserved.

Preliminary data sheet

Rev. 1.01 — 15 November 2007

36 of 68

Page 36
Image 36
NXP Semiconductors LPC2919, LPC2917 user manual ADC pin description, ADC block diagram, Analog to digital converter pins