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Fujitsu MB39A104 manual Block Diagram, bias, 1.24

Models: MB39A104

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MB39A104

■BLOCK DIAGRAM

−INE1	10	VREF		Error	L priority		CH1	1	VCCO
		VREF			PWM

	10 ∝A		−	Amp1
CS1 11			+		+ Comp.1		Drive1
			+		+		Drive1
			+		+	Pch		3	OUT1
		1.24 V			−	Pch		3	OUT1
		1.24 V	L priority
			L priority
FB1	9					IO = 200 mA
						IO = 200 mA
						at VCCO	= 12 V
						Current	−	4	VS1
						Current		4	VS1
						Protection	+	5	ILIM1
						Logic		5	ILIM1
						Logic
DTC1	6
−INE2	15	VREF		Error	L priority		CH2
		VREF		Error
	10 ∝A		−	Amp2	PWM
CS2 14			+		+ Comp.2		Drive2
CS2 14			+		+	Pch		22 OUT2
		1.24 V			−	Pch		22 OUT2
		1.24 V	L priority
			L priority
FB2 16						IO = 200 mA
						IO = 200 mA
DTC2 19						at VCCO	= 12 V
						Current	−	21	VS2
		H: at SCP	H priority			Current		21	VS2
		H: at SCP	H priority			Protection	+	20	ILIM2
			SCP			Protection	+	20	ILIM2
			SCP			Logic
			Comp.			Logic
			Comp.
				+
				+
				−
				(3.1 V)		H: at OCP	VCC − 5 V	2	VH
							VCC − 5 V
							VH
							VH
		SCP					Bias
		Logic					Voltage
CSCP	8				2.5 V			23 GNDO
					2.5 V	Error Amp Power Supply
		UVLO			1.5 V	Error Amp Power Supply
					1.5 V

			H:UVLO			Error Amp Reference		7	VCC
			H:UVLO
			release
			release		bias	1.24 V
					bias	1.24 V	Power
		OSC					Power	24 CTL
		OSC			Accuracy	VREF	VR1 ON/OFF	24 CTL
					Accuracy		CTL
					±1%		CTL
					±1%
					5.0 V
		12	13		17		18
		RT CT			VREF		GND

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Fujitsu MB39A104 manual Block Diagram, bias, 1.24

Contents

FEATURES FUJITSU SEMICONDUCTOR DATA SHEETDESCRIPTION PACKAGEMB39A104 PIN ASSIGNMENTSPIN DESCRIPTION SymbolMB39A104 Pin NoBLOCK DIAGRAM MB39A104bias 1.24ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONSSymbol SymbolELECTRICAL CHARACTERISTICS MB39A104Parameter Pin NoSymbol MB39A104Continued ParameterTYPICAL CHARACTERISTICS MB39A104ICCmA VREFVMB39A104 vs. Timing ResistorTriangular Wave Oscillation Frequency vs. Ambient Temperature ContinuedError Amplifier, Gain, Phase vs. Frequency Power Dissipation vs. Ambient TemperatureMB39A104 ContinuedFUNCTIONS 1. DC/DC Converter Functions3 Error amplifier block Error Amp1, Error Amp2 MB39A1042. Control Function 3. Protective Functions1 Timer-latch overcurrent protection circuit block OCP 2 Timer-latch short-circuit protection circuit SCP Logic, SCP CompSETTING THE TRIANGULAR OSCILLATION FREQUENCY SETTING THE OUTPUT VOLTAGEMB39A104 SETTING THE SOFT-START AND DISCHARGE TIMES MB39A104CH ON/OFF signal MB39A104L priority L ON, H OFFWithout Setting Soft-Start Time TREATMENT WITHOUT USING CS TERMINALMB39A104 1. Setting Timer-Latch Overcurrent Protection Detection Current ABOUT TIMER-LATCH PROTECTION CIRCUITMB39A104 Method to detect by current when external FETQ1 is turned on MB39A104Overcurrent Detection Function Operating Range Overcurrent Protection Circuit Range of OperationTimer-latch short-circuit protection circuit MB39A104TREATMENT WITHOUT USING CSCP TERMINAL RESETTING THE LATCH OF EACH PROTECTION CIRCUITTreatment without using CSCP MB39A104I/O EQUIVALENT CIRCUIT MB39A104H ON Power ON MB39A104L OFF Standby mode V TH = 1.4PARTS LIST MB39A104MB39A104 SELECTION OF COMPONENTSPch MOS FET MB39A104 MB39A104 InductorsMB39A104 IO ≥MB39A104 MB39A104 Flyback diodeSmoothing Capacitor MB39A1042 π ⋅ 500 ⋅ 10 3 ⋅ 82 ⋅ 10 − MB39A104 ⋅ 102 π ⋅ 500 ⋅ 10 3 ⋅ 0.050 − 0.491 ⋅ 2 π ⋅ 500 ⋅ 10 3 ⋅ 0.033 − 0.364 ⋅REFERENCE DATA MB39A104Continued 10 mSwitching Wave Form CH1 Switching Wave Form CH2MB39A104 ContinuedUSAGE PRECAUTION ORDERING INFORMATIONMB39A104 Take appropriate static electricity measuresPACKAGE DIMENSIONS MB39A104MB39A104 FUJITSU LIMITEDF0308  FUJITSU LIMITED Printed in Japan

■BLOCK DIAGRAM

bias

1.24 V