CYS25G0101DX-ATC Evaluation Board User’s Guide
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5.4 “Parallel Line Loopback” (TEST0) Mode
In Parallel Line Loopback mode, the parallel output buffers are internally linked to the parallel input buffers. Figure 7 shows the data
path (bold line) of the Parallel Line Loopback mode. In this test mode, the internal RX CDR PLL and TX PLL can be tested by different
configurations.

5.4.1 Test the Internal RX CDR PLL Only

1. TEST0, jumper J6 must be shorted
2. SW1-5 (LOOPTIME) must be in ON position
3. All other dip switches must be in their default positions (see Table 4)
4. Apply the Testing Hookup illustrated in Figure 8 to Figure 10 for the measurement

5.4.2 Test the Internal RX CDR PLL and TX PLL

1. TEST0, jumper J6 must be shorted
2. All dip switches must be in their default positions (see Tabl e 4)
3. Disconnect CLKVCC (P2), remove the 155.52-MHz oscillator, place C400 on C402 and C401 on C403 positions (see Table
1, jumpers J17 and J18 for details)
4. Apply the Testing Hookup illustrated in Figure 11 for the measurement
Figure 7. Parallel Loopback (TEST0) Mode Data Path
TXD
15:0
TX PLL
x16
/16
RXD
15:0
REFCLK RXCLKOUT
SHIFTER RX CDR
PLL
TXCLK
Input
Register
Output
Register
FIFO
(5byte) SHIFTER
TXCLKIN
/16
DIAGLOOP
(SW1-2) = OFF
LINELOOP
SW1-3 = OFF
LOOPA
SW1-4 = OFF
IN±
OUT±
JUMPER J6 (TEST0) = CLOSED
TXD
15:0
TX PLL
x16
/16
RXD
15:0
REFCLK RXCLKOUT
SHIFTER RX CDR
PLL
TXCLK
Input
Register
Input
Register
Output
Register
Output
Register
FIFO
(5byte)
FIFO
(5byte) SHIFTER
TXCLKIN
/16
DIAGLOOP
(SW1-2) = OFF
LINELOOP
SW1-3 = OFF
LOOPA
SW1-4 = OFF
IN±
OUT±
JUMPER J6 (TEST0) = CLOSED
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