Store Inhibit or Power Up Recall

					STK11C88
STORE INHIBIT or Power Up RECALL
Parameter	Alt	Description	STK11C88			Unit
Parameter	Alt	Description	Min	Max		Unit
			Min	Max
tHRECALL [10]	tRESTORE	Power up RECALL Duration		550		μs
tSTORE [6]	tHLHZ	STORE Cycle Duration		10		ms
VRESET		Low Voltage Reset Level		3.6		V
VSWITCH		Low Voltage Trigger Level	4.0	4.5		V

Figure 9. STORE INHIBIT/Power Up RECALL

VCC

VSWITCH

VRESET

STORE INHIBIT

POWER-UP RECALL

tHRECALL

DQ (DATA OUT)

Notes

10. tHRECALL starts from the time VCC rises above VSWITCH.

Document Number: 001-50591 Rev. **

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Contents

Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion Court Output Enable, Active LOW. The active LOW Pin ConfigurationsWrite Enable Input, Active LOW. When the chip is enabled Power Supply Inputs to the Device Sram Read Hardware Recall Power UpDevice Operation Sram Write Noise Considerations Low Average Active PowerHardware Protect Best Practices Read Sram Output Data 0x03E0 Software STORE/RECALL Mode Selection A13 A00x0E38 Read Sram Output Data Read Sram Output Data 0x303F Operating Range DC Electrical CharacteristicsMaximum Ratings Data Retention and Endurance AC Test Conditions CapacitanceThermal Resistance Sram Read Cycle AC Switching CharacteristicsSwitching Waveforms Parameter Description 25 ns 45 ns Unit Cypress Alt Min Max Parameter Description 25 ns 45 ns Unit Cypress Alt Min Sram Write CycleMin Max Parameter Store Inhibit or Power Up Recall Parameter Alt Description STK11C88 Unit Min Max Software Controlled STORE/RECALL Cycle Parameter Alt Description 25 ns 45 ns Unit Min Max Part Numbering Nomenclature STK11C88 N F 25 I TR Ordering Information Package Diagrams Pin 300 mil Soic Pin 330 mil Soic New data sheet Sales, Solutions and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History