256 Kbit (32K x 8) AutoStore nvSRAM
Features
■35 ns and 45 ns access times
■Automatic nonvolatile STORE on power loss
■Nonvolatile STORE under Hardware or Software control
■Automatic RECALL to SRAM on power up
■Unlimited Read/Write endurance
■Unlimited RECALL cycles
■1,000,000 STORE cycles
■100 year data retention
■Single 3.3V+0.3V power supply
■Commercial and Industrial Temperatures
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■RoHS compliance
Functional Description
The Cypress
Logic Block Diagram |
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| VCC | VCAP |
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| Quantum Trap |
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| 512 X 512 |
| POWER |
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A5 |
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| STORE |
| CONTROL |
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A6 | DECODER |
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A7 |
| RECALL |
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A8 |
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| STORE/ |
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A9 |
| STATIC RAM |
| RECALL | HSB |
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| ARRAY |
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A11 |
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| CONTROL |
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ROW |
| 512 X 512 |
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A12 |
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A13 |
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A14 |
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| SOFTWARE |
| A13 - A0 |
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| DETECT |
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DQ0 |
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| COLUMN I/O |
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DQ1 | BUFFERS |
| COLUMN DEC |
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DQ2 |
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DQ3 |
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DQ4 |
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INPUT |
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DQ5 |
| A0 A1 A2 A3 A4 A10 |
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DQ6 |
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DQ7 |
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| OE |
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| CE |
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| WE |
Cypress Semiconductor Corporation | • | 198 Champion Court | • | San Jose, CA | • | |||
Document Number: |
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| Revised January 29, 2009 |
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