Cypress STK14C88-3 Hardware STORE Cycle

STK14C88-3

Document Number: 001-50592 Rev. ** Page 13 of 17

Hardware STORE Cycle

Parameter Alt Description STK14C88-3 Unit

Min Max

PHSB

HLHX

Hardware STORE Pulse Width 15 ns

DHSB [16, 20]

RECOVER,

HHQX

Hardware STORE High to Inhibit Off 700 ns

HLBL

Hardware STORE Low to STORE Busy 300 ns

Switching Waveforms

Figure 13. Hardware STORE Cycle

3+6%

Note

20.t

DHSB

is only applicable after t

STORE

is complete.

[+] Feedback

Contents

Main STK14C88-3 256 Kbit (32K x 8) AutoStore nvSRAM , Features Functional Description Logic Block Diagram Pin Configurations STK14C88-3 Device Operation AutoStore SRAM Read SRAM Write STK14C88-3 Hardware STORE (HSB) Operation Hardware RECALL (Power Up) Software STORE Software RECALL Preventing STORE Hardware Protect Noise Considerations Low Average Active Power Best Practices Maximum Ratings Operating Range DC Electrical Characteristics STK14C88-3 Data Retention and Endurance Capacitance Thermal Resistance AC Test Conditions AC Switching Characteristics SRAM Read Cycle Page AutoStore or Power Up RECALL Software Controlled STORE/RECALL Cycle / t Hardware STORE Cycle STK14C88-3 Ordering Information Part Numbering Nomenclature STK14C88- 3N F 45 I TR Document Number: 001-50592 Rev. ** Page 15 of 17 Package Diagrams [+] Feedback 17 32 SEATINGPLANE 51-85058 *A Package Diagrams Document Number: 001-50592 Rev. ** Page 16 of 17 [+] Feedback Figure 15. 32-Pin (600 Mil) PDIP (51-85018) (continued) Document History Page Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC Solutions