![](/images/new-backgrounds/1239603/239603137x1.webp)
| SCL | 24 | I | Serial bus clock | |||||||
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| SDA | 23 | I/0 | Serial bus address and data input and output pin. | |||||||
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| Open drain output. | ||||||
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| GCK | 7 | O | General Purpose Clock. Clock frequency is determined by the state of | |||||||
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| GOUT[1:0] when | RST | pin is low. | ||||
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| 00 : | 40.5 MHz clock output. | |||||
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| 0 | 1: | 54.0 MHz clock output. | ||||
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| 1 | 0: | 67.5 Mhz clock output. | ||||
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| 1 | 1: | 81.0 MHz | ||||
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| CK27 | 9 | O | 27 MHz clock output pin. | |||||||
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| ACK | 25 | I/O | 384*fs Audio clock output pin. | |||||||
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| Controlled by CR2[1:0] | ||||||
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| 0 | 0: | 384 * 44.1 KHz (16.934MHz) clock output. | ||||
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| 0 | 1: | 384 * 48.0 KHz (18.432MHz) clock output. | ||||
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| 1 | 0: | 384 * 88.2 KHz (33.868MHz) clock output. | ||||
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| 1 | 1. | 384 * 96.0 KHz (36.864MHz) clock output. | ||||
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| XIN | 2 | I | 27 Mhz oscillator input | |||||||
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| XOUT | 1 | O | 27 Mhz oscillator output | |||||||
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| 6 | I | Active low chip reset input. Chip is in the power down mode when the | ||||||
| RST | ||||||||||
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| RST is low. |
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| GOUT1 | 44 | O | Dual function pin. | |||||||
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| GCK frequency select pin when | RST | is low. | ||||
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| General purpose output pin when RST is high | ||||||
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| GOUT0 | 43 | I | Dual function pin. | |||||||
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| GCK frequency select pin when | RST | is low. | ||||
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| General purpose output pin when RST is high | ||||||
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| VDD | 10, 22, 5 | +5V | Digital power supply. | |||||||
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| VSS | 8, 17, 26, | GND | Digital ground | |||||||
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| 30, 34, |
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| 41, 42, 4 |
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| VDDA | 29, 32, | +5V | Analog video power supply. | |||||||
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| 36. |
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