3 AP-135 TEL Placement, AP-134 Top View | Dell W-AP135, W-AP134

Figure 4: AP-134 Top View

Figure 5: AP-134 Right View

Figure 6: AP-134 Bottom View

3.2.3 AP-135 TEL Placement

This section displays all the TEL locations of the Aruba AP-135. The AP-134 requires a minimum of 5 TELs to be applied as follows:

3.2.3.1To detect opening of the chassis cover:

1.Spanning the bottom and top chassis covers and placed in the front left corner

13

Image 13

Dell W-AP135, W-AP134 manual 3 AP-135 TEL Placement, AP-134 Top View

Contents

Fips 140-2 Non-Proprietary Security Policy Page Security Levels Physical Security Aruba Dell Relationship Acronyms and AbbreviationsModes of Operation Operational Environment Logical Interfaces Services Aruba Dell Relationship IntroductionAcronyms and Abbreviations CPSec SHA AP-134 Product OverviewPhysical Description Aruba Part Number Dell Corresponding Part Number PWR AP-134 Indicator LEDs Label Function Action StatusENET0 ENET1 AP-135 AP-135 Indicator LEDs Label Function Action Status Security Levels Module ObjectivesPhysical Security Applying TELs AP-134 Front view 2 AP-134 TEL Placement AP-134 Top View 3 AP-135 TEL Placement AP-135 Front view AP-135 Top view Inspection/Testing of Physical Security Mechanisms Modes of Operation Configuring Remote AP Fips Mode Enable Fips mode on the AP. This accomplished by going to Configuring Remote Mesh Portal Fips Mode Configuring Remote Mesh Point Fips Mode Operational Environment Verify that the module is in Fips mode Fips 140-2 Logical Interface Module Physical Interface Logical Interfaces Crypto Officer Authentication Roles, Authentication and ServicesRoles Wireless Client Authentication User AuthenticationStrength of Authentication Mechanisms Authentication Mechanism Strength WPA2-PSK Crypto Officer Services ServicesWPA2 PSK KEK PMK User ServicesPTK Eapol MIC Unauthenticated Services Wireless Client Services ∙ FTP ∙ Tftp ∙ NTP Non-FIPS Approved Algorithms Cryptographic Algorithms Hmac Critical Security Parameters RNG AES-CCM PSK GTK GMK Self Tests For an AES Atheros hardware Post failure