11.2 Data Acquisition Circuit Register Map

 

 

 

 

 

 

WRITE

(Blank bits are unused and have no effect)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

7

6

5

4

 

3

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

STRTAD

 

RSTBRD

 

RSTDA

 

RSTFIFO

CLRDMA

CLRT

CLRD

CLRA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

H3

 

H2

 

H1

 

H0

L3

L2

L1

L0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

SCANEN

G1

G0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

CKSEL1

 

CKFRQ1

 

CKFRQ0

 

ADCLK

DMAEN

TINTE

DINTE

AINTE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

FT5

 

FT4

FT3

FT2

FT1

FT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

DA7

 

DA6

 

DA5

 

DA4

DA3

DA2

DA1

DA0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

DACH1

 

DACH0

 

 

 

 

 

DA11

DA10

DA9

DA8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

PA7

 

PA6

 

PA5

 

PA4

PA3

PA2

PA1

PA0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

PB7

 

PB6

 

PB5

 

PB4

PB3

PB2

PB1

PB0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

PC7

 

PC6

 

PC5

 

PC4

PC3

PC2

PC1

PC0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

DIOCTR

 

 

 

 

 

DIRA

DIRCH

 

 

DIRB

DIRCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

CTRD7

 

CTRD6

 

CTRD5

 

CTRD4

CTRD3

CTRD2

CTRD1

CTRD0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

CTRD15

 

CTRD14

 

CTRD13

 

CTRD12

CTRD11

CTRD10

CTRD9

CTRD8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

CTRD23

 

CTRD22

 

CTRD21

 

CTRD20

CTRD19

CTRD18

CTRD17

CTRD16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

CTRNO

 

LATCH

 

GTDIS

 

GTEN

CTDIS

CTEN

LOAD

CLR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ

(Blank bits are unused and read back as 0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

7

 

6

 

5

 

4

 

3

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

AD7

 

AD6

 

AD5

 

AD4

 

AD3

 

AD2

 

AD1

AD0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

AD15

 

AD14

 

AD13

 

AD12

 

AD11

 

AD10

 

AD9

AD8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

H3

 

H2

 

H1

 

H0

 

L3

 

L2

 

L1

L0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

STS

 

SD

 

WAIT

 

DACBSY

 

OVF

 

SCANEN

 

G1

G0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

CKSEL1

 

CKFRQ1

 

CKFRQ0

 

ADCLK

 

DMAEN

 

TINTE

 

DINTE

AINTE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

FT5

 

FT4

 

FT3

 

FT2

 

FT1

FT0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

FD5

 

FD4

 

FD3

 

FD2

 

FD1

FD0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

DMAINT

 

TINT

 

DINT

 

AINT

 

ADCH3

 

ADCH2

 

ADCH1

ADCH0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

PA7

 

PA6

 

PA5

 

PA4

 

PA3

 

PA2

 

PA1

PA0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

PB7

 

PB6

 

PB5

 

PB4

 

PB3

 

PB2

 

PB1

PB0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

PC7

 

PC6

 

PC5

 

PC4

 

PC3

 

PC2

 

PC1

PC0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

DIOCTR

 

 

 

 

 

DIRA

 

DIRCH

 

 

 

DIRB

DIRCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

CTRD7

 

CTRD6

 

CTRD5

 

CTRD4

 

CTRD3

 

CTRD2

 

CTRD1

CTRD0

 

 

 

 

 

 

 

 

 

 

 

13

 

CTRD15

CTRD14

CTRD13

CTRD12

CTRD11

CTRD10

 

CTRD9

CTRD8

 

 

 

 

 

 

 

 

 

 

14

 

CTRD23

CTRD22

CTRD21

CTRD20

CTRD19

CTRD18

CTRD17

CTRD16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

REV7

 

REV6

 

REV5

 

REV4

 

REV3

 

REV2

 

REV1

REV0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Prometheus CPU User Manual V1.44

Page 32

Page 32
Image 32
Diamond Systems PR-Z32-EA-ST, PR-Z32-E-ST user manual Data Acquisition Circuit Register Map, AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

PR-Z32-E-ST, PR-Z32-EA-ST specifications

The Diamond Systems PR-Z32-EA-ST and PR-Z32-E-ST are pioneering solutions in the realm of embedded computing systems, designed to meet the challenging demands of various industrial applications. These boards harness advanced technologies and a comprehensive feature set to ensure exceptional performance, flexibility, and reliability.

At the heart of the PR-Z32 series is a robust processor architecture that combines efficiency with processing power. The systems are built around the Zynq-7000 SoC (System on Chip), which integrates a dual-core ARM Cortex-A9 processor with Xilinx FPGA technology. This hybrid architecture provides the ability to run complex algorithms and custom logic concurrently, making the boards ideal for applications requiring intense computational tasks such as image processing, data acquisition, and real-time control.

One of the main features of the PR-Z32-EA-ST and PR-Z32-E-ST is their versatility. Both variants support a wide range of I/O options, including USB, Ethernet, CAN, and serial interfaces. This range of connectivity allows for integrations with various sensors, actuators, and other peripheral devices, making it suitable for industrial automation, robotics, and IoT projects. The inclusion of multiple GPIO pins also enhances the capability of the boards to interface with additional hardware.

In terms of performance, the PR-Z32 series supports substantial amounts of on-board memory, which can be essential for applications requiring the storage and processing of large datasets. The configurations are often customizable, allowing users to select the appropriate amount of RAM and on-board flash memory for their specific applications.

Reliability is a critical characteristic of the Diamond Systems PR-Z32 series. The boards are built to withstand adverse environmental conditions, making them suitable for deployment in industrial environments. They are often designed to operate over a wide temperature range, ensuring functionality in both hot and cold climates. Additionally, the boards are compliant with various industry standards, assuring users of their robustness and durability.

Moreover, the PR-Z32-EA-ST and PR-Z32-E-ST support real-time operating systems (RTOS) and conventional operating systems such as Linux. This support provides developers with the flexibility to choose the best environment for their applications, whether they require real-time performance or full-fledged operating system features.

In conclusion, the Diamond Systems PR-Z32-EA-ST and PR-Z32-E-ST are formidable options for those seeking powerful, versatile, and reliable embedded computing solutions. With their advanced SoC architecture, flexible I/O options, extensive memory configurations, and environmental resilience, these boards are well-equipped to tackle the challenges of modern industrial applications.