Principles of Operation

Printhead Drive Circuit

The printhead drive circuit receives two types of signals: image data and the pulse length control signals. Image data is created in the CPU, transferred to the gate array, and latched to the printhead. The pulse length control signal is set by the CPU. The pulse length is adjusted referring to the voltage of the +35 V line. These two types of signals are sent to the printhead to print each dot. Figure 6-29 shows the printhead drive circuit.

+35VDC

+35VDC

CPU (IC2Cl)

 

GA (IC4)

1

HEAD

I

DO-7 DO-7

HDP

P51

P83HPW

HDNl

HDkl9

Figure 6-29. Printhead Drive Circuit
Parallel Interface Circuit

The parallel interface circuit controls the data flow from the host computer. When am signal is sent from the host computer, the data is latched into the gate array (E05A66YA). Data is transmitted until a BUSY signal is sent back automatically to the host computer to stop the data. Then, the gate array outputs an B8’ signal to P82 (the interrupt signal port) of the CPU. The CPU then reads the data latched into the gate array and, on completion ofthe reading, resets the BUSY signal to enable the host computer to send more data. Figure 6-30 shows the parallel interface circuit.

Parallel I/F

E05A55YA(IC4)

 

CPU (IC2Cl)

 

 

 

 

 

DO-7

 

 

 

DINO-7

DATAO-7

 

DO-7

 

 

 

 

 

 

 

 

 

 

STB

IBF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

- - - - - - - - q-----------

 

 

STROBE

I

 

 

P82

 

 

 

 

 

 

I

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

 

 

 

 

II

 

 

 

 

B U S Y +

 

----,,,,A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUSY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 6-30. Parallel Interface Circuit

Epson FX-870/1170

6-29