CHAPTER 5: OPERATION AND FUNCTION OF S5U1C63000H2

(2) Interrupt in standby mode

In the standby mode, interrupt requests from the target system is reserved. The interrupt while the monitor program is being executed is accepted at the execution of the target program. For instance, when an interrupt request from the target system is generated while breaking, the interrupt is accepted immediately after the target program restarts if the interrupt is enabled in the S1C63000 CPU.

(3)Interrupt at single step operation

Interrupts during single step operation can be enabled or disabled using the MD command. Each operation is as follows.

•When interrupt is enabled

If an interruption request is generated while a target program step is executed by the S or N com- mands, the interrupt processing is done at the time of the instruction execution, and the execution stops after fetching the vector address of the interrupt. Therefore, next single step operation executes the interrupt handler routine. When the HALT or SLP instructions are executed by the S or N com- mands, the commands are executed until a interrupt is occurred. In this status, a forced break input from the host computer suspends the execution.

•When interrupt is disabled

Interrupt processing are not executed by the S command. Therefore, the execution of the HALT or SLP instructions is immediately suspended, and the program counter indicates an address next to the HALT or SLP instructions. The N command operates similar to the S command in the execution of the main routine, however, it enables interrupts regardless of the setting by the MD command in the execution of the sub-routine.

(4)Data read from undefined RAM area

When a data RAM (ROM) area or an I/O area that is not available in the actual IC chip is read, the read data becomes indefinite. Read data from the actual IC is also indefinite, however it is different from the S5U1C63000H2.

(5)Detection of SP1 incorrect stack access

It is possible to detect any incorrect stack access to out of SP1 area by specifying the SP1 area with the BSP command.

The S1C63000 CPU has a queue register and takes stack value in advance in order to make high speed process of the stacking operation for the CALR instruction and interrupts. Therefore, when a value is returned from the top address of the stack, it takes the stack value beyond the top address and write it into the queue register. This operation works without any problem, however, the queue register has an indefinite value. In order not to make this process incorrect access, it is necessary to add three addresses onto the real using SP1 area.

(6)Data read break

In the execution of "INT addr6" instruction, setting break on the data read condition may break program running, because dummy read cycle of a memory specified by addr6 operand is added. For instance, when the break at read cycle is set by the break data set command (BD), the dummy read hits the break condition.

S5U1C63000H2 MANUAL

EPSON

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(S1C63 FAMILY IN-CIRCUIT EMULATOR)