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DIM code checkpoints

The Device Initialization Manager (DIM) gets control at various times during BIOS POST to initialize different system buses. The following table describes the main checkpoints where the DIM module is accessed.

Checkpoint

Description

 

 

2A

Initialize different buses and perform the following

 

functions:

 

Reset, Detect, and Disable (function 0) — Disables all

 

 

device nodes, PCI devices, and PnP ISA cards. It also

 

 

assigns PCI bus numbers.

 

Static Device Initialization (function 1) — Initializes all

 

 

static devices that include manual configured onboard

 

 

peripherals, memory and I/O decode windows in PCI-PCI

 

 

bridges, and noncompliant PCI devices. Static resources

 

 

are also reserved.

 

Boot Output Device Initialization (function 2) — Searches

 

 

for and initializes any PnP, PCI, or AGP video devices.

 

 

 

38Initialize different buses and perform the following functions:

Boot Input Device INitialization(function 3) — Searchesfor and configures PCI input devices and detects if system has standard keyboard controller.

IPL Device Initialization (function 4) — Searches for and configures all PnP and PCI boot devices.

General Device Initialization (function 5) — Configures all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices.

ACPI runtime checkpoints

ACPI checkpoints are displayed when an ACPI-capable operating system either enters or leaves a sleep state. The following table describes the types of checkpoints that may occur during ACPI sleep or wake events:

Checkpoint

Description

 

 

AC

First ASL checkpoint. Indicates that the system is running in

 

ACPI mode.

AA

System is running in APIC mode.

 

 

01, 02, 03, 04, 05

Entering sleep state S1, S2, S3, S4, or S5.

 

 

10, 20, 30, 40, 50

Waking from sleep state S1, S2, S3, S4, or S5.

 

 

BIOS

The settings in the BIOS Setup utility are not retained

Replace the CMOS battery. For instructions, see “Replacing the CMOS battery” on page 53.

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