Post Codes
These tables describe the Post Codes and components of the POST process.
Sec:
| NO_EVICTION_MODE_DEBUG EQU | 1 (CommonPlatform\sec\Ia32\SecCore.inc) | ||
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| 0x | MTRR setup |
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| C2 |
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| 0x | Enable cache |
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| C3 |
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| 0x | Establish cache tags | ||
| C4 |
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| 0x | Enter NEM, Place the BSP in No Fill mode, set CR0.CD = 1, CR0.NW = 0. | ||
| C5 |
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| 0xCF | Cache Init Finished |
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Memory: |
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| DEBUG_BIOS EQU | 1 (Chipset\Alviso\MemoryInitAsm\IA32\IMEMORY.INC) | ||
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| 0x |
| First memory check point | |
| A0 |
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| 0x |
| Enable MCHBAR |
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| 01 |
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| 0x |
| Check for DRAM initialization interrupt and reset fail | |
| 02 |
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| 0x |
| Verify all DIMMs are DDR or DDR2 and unbuffered | |
| 03 |
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| 0x |
| Detect an improper warm reset and handle | |
| 04 |
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| 0x |
| Detect if ECC | |
| 05 |
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| 0x |
| Verify all DIMMs are single or double sided and not asymmetric | |
| 06 |
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| 0x |
| Verify all DIMMs are x8 or x16 width | |
| 07 |
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| 0x |
| Find a common CAS latency between the DIMMS and the MCH | |
| 08 |
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| 0x |
| Determine the memory frequency and CAS latency to program | |
| 09 |
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| 0x |
| Determine the smallest common TRAS for all DIMMs | |
| 10 |
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| 0x |
| Determine the smallest common TRP for all DIMMs | |
| 11 |
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| 0x |
| Determine the smallest common TRCD for all DIMMs | |
| 12 |
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| 0x |
| Determine the smallest refresh period for all DIMMs | |
| 13 |
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Chapter 4 | 161 |
