VERTICAL AND HORIZONTAL SYNC CIRCUIT DESCRIPTION.

Composite

 

Vertical Sync

{ Horizontal Sync

Sync

 

 

 

Sync Interface 2 Comparators

For Interlaced Vertical Sync.

+

 

 

 

 

 

Vertical Sync To Horizontal Cycle Synchronization and Composite Sync Decoder

To LA7851 pin 19

To LA7851 pin 1

Composite sync or separate vertical and horizontal sync are buffered by two comparators in the sync interface circuit. A vertical sync synchronization circuit is used to insure a stable raster and functions as a sync separator.

The synchronization circuit is bypassed, for interlaced vertical sync, because this circuit rejects the half horizontal line time variation used to generate the interlaced vertical raster.

 

 

 

 

 

Vertical Sync

 

Horizontal Sync

 

FBP

 

 

 

 

 

 

 

 

 

 

+12V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7.15K

 

 

+

9

15.8K

68.1K

15.8K

 

 

 

 

 

 

 

 

366

7.15K

14

1/4

 

353

354

360

 

 

 

 

 

 

 

 

 

364

 

LM339

8

 

2.1-2.4VDC Hs

 

 

0

 

Interlace (15KHz)

 

355

 

 

 

 

 

 

 

1K

4.6Vpp 58,D6

 

 

364

 

10uF

 

 

 

 

 

 

1.5-2VDC

59,D6

 

 

 

 

+

 

 

 

 

 

 

357

 

 

 

 

1K

259

1.8K

 

0

 

 

+

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

246

 

47nF

257

 

318

 

1/4

 

 

 

 

 

 

 

 

 

LM339

 

 

 

 

 

 

 

 

254

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

355

 

 

 

 

 

 

 

 

+12V

 

 

6.8K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.92K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

358

 

 

 

 

 

 

22K

 

 

321

 

 

 

356

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

323

 

 

6.8K

 

200K

.05VDC

Vs,Hs

 

 

 

 

1.8K

 

 

4

 

 

3

322

 

246

 

 

 

 

 

 

 

 

 

7V pp 60,C5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

325

 

270

 

1/4

2

 

 

PN2222

 

 

 

 

 

 

 

 

5

LM339

 

 

 

 

 

 

 

 

GND 0

 

326

+

 

355

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

328

 

 

 

 

 

 

 

255

 

 

 

 

 

 

 

270

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

1/4

 

 

 

 

 

 

 

 

 

1.8K

 

330

 

LM339

 

 

100K

PN2222

 

 

 

 

 

 

7 +

 

355

 

 

257

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

331

 

.14-.16V

 

12

 

.047uF

200K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Hs

Vs

 

 

270

 

 

 

318

256

 

254

 

 

Horizontal

 

 

327

 

 

 

33K

 

 

VC

VC Vertical

 

 

 

 

 

 

 

 

 

 

Sync

1

2 Sync

 

GND

 

 

 

 

 

GND

 

247

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The sync interface comparators are biased to .15 volts, by resistors 323 & 327 , to permit receiving low level sync signals such as RS170. For low level composite sync, the vertical and horizontal lines are tied together and jumper 328 is left off. For normal amplitude sync, (greater than 2.3 volts) resistors 325 & 326 form an attenuator to protect the sync interface comparators and normalize the sync amplitude. This combination also reduces noise sensitivity since the sync voltage amplitude is low at the comparator input which slows the comparator response and acts as a low pass filter.

For the interlaced sync case, the pullup resistor 321 is left off and the voltage divider resistors 246 and 257 act as the pullup. Also the vertical sync synchronization comparators are disabled by changing the input resistors to bias the comparators in the high output state and resistor 366 is left off. Capacitor 254 acts as a sync separator for composite interlaced sync. Capacitor 259 and jumper 364 are used to couple the composite sync to the LA7851 vertical sync input pin 19.

The vertical sync synchronization window comparator generates a pulse, a little after the midpoint of each horizontal cycle. This pulse is shorted to GND by transistors 255 except when vertical sync is active. The two transistor circuit permits using either positive or negative pulses for vertical sync.

Capacitor

318

couples the vertical sync pulses to

transistors

 

 

 

&

 

. When no sync pulse is present,

 

254

255

transistor

 

 

 

is

turned

on by resistor

 

 

. For a

255

246

negative vertical

 

sync pulse, transistor

 

 

is turned off

 

 

255

by the negative pulse applied to resistor

 

 

 

 

and the

 

257

 

window comparator pulse is allowed to be the vertical sync pulse. For positive vertical sync pulse, transistor 254 is turned on by resistor 247 & 256 , which shorts the base of transistor 255 to GND also allowing the window comparator pulse to act as the sync pulse.

A sawtooth waveform is produced on integrating capacitor 358 by applying the flyback pulse to resistors

360& 357 . This sawtooth waveform is connected to two

comparators which are biased by resistors 353 ,

356 , 354 , & 360 such that both comparator outputs are high between 1.8 volts to 2.3 volts. This circuit would produce a pulse on both the positive and negative slope parts of the sawtooth waveform. Resistor 357 eliminates the output pulse on the negative slope by introducing part of the flyback pulse to pin 8 which keeps the comparator from going high at this time. Resistors 364 & 366 act as a pullup for the window comparator and apply a 6 volt bias to the vertical sync input, LA7851 pin 19. At 6 volts, the vertical sync input is inactive. It becomes active only when the window comparator output and the ± sync transistors are all high.

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Genius 1993, ISO XFR-75W, 2093, 1493, 2793, 3693, 1793, ISO XFR-100W manual Vertical and Horizontal Sync Circuit Description

2093, 1493, ISO XFR-75W, 3693, 2793 specifications

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