CIRCUIT DESCRIPTION
UHF SYNTHESIZER DESCRIPTION
(1) CLOCK |
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| Serial Input + Program Latches |
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(2) DATA |
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| VDD (7, 15, 20) | ||||||||||||||||||||||
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(3) STROBE |
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(4, 12) Vss |
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| ÷N | ÷A |
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| FMOD F INC |
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(5) RF |
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| ÷64/65 |
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| Fractional |
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| Prescaler |
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| IN |
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| Main Dividers |
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| Modulus |
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| Prescaler |
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| Accumulator |
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(6) RFIN |
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| Control |
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| RF (17) | |||||||||||||||
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(19) TEST |
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| f V |
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| RN (16) | |||||||||
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| Normal |
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| Output |
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| Main |
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| Charge |
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| Pump |
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| Detector |
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| PHP (14) | |||||||||
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| fR |
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| Main |
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| Output |
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| Reference |
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| Charge |
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| Select |
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(8) REF |
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| Reference Divider |
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| ÷2 | ÷2 | ÷2 |
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| Integral |
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| Output |
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| IN |
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| PHI (13) | |||||||
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| ÷R |
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| LOCK (18) | ||||
(10) AUX |
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| IN |
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| PHA (11) | |
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| RA (9) |
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| V |
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| SSA |
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another. Programming is performed using the SPI serial port of the microcontroller described in Section
3.3.1.The input to the internal shift register of these devices is the DATA pin (U800/U801) or SDI pin (U802), and the output of the last shift register stage in U800 and U801 is the QS pin. Therefore, serial data on the Data line from the audio/logic board (J201, pin 14) is first shifted into U801, then U800, and then U802.
Data is clocked through the devices by the CLOCK signal (J201, pin 13) when the STROBE input (J201, pin 12) is high and latched when it goes low. Synthesizer IC U804 is also programmed by the SPI port. However, data does not pass through the other devices, and it is controlled by different STROBE signal (J201, pin 1).
NOTE: The receiver block diagram is shown in Figure
3.8.1 FRONT END FILTER
The receive signal is fed from the antenna switch circuit on the PA board to the receiver front end on the RF board. The signal is fed through a section of microstrip that is part of a
The receive signal is applied to a
| February 2001 |
Part No. |