CIRCUIT DESCRIPTION
800/900 MHz SYNTHESIZER DESCRIPTION
divide number. In this example the
+15,424 + .75 or 16,269.75. The VCO frequency of
813.4875 MHz divided by 16,269.75 equals 50 kHz which is the fR input to the phase detector.
NOTE: The formulas for calculating the “N” and “A” divide numbers are described in Section 4.3.5.
3.10.7 LOCK DETECT
When the synthesizer is locked on frequency, the LOCK output of U804 (pin 18) is a logic high voltage. Then when the synthesizer is unlocked, this voltage is low. A locked condition exists when the phase difference at the TCXO input is less than one cycle.
3.10.8 CHARGE PUMP
The charge pump circuit in U804 charges and discharges
3.10.9SHIFT REGISTER (U800, U801) AND DIGITAL POTENTIOMETER (U802) PROGRAMMING
Shift register U800 functions as an I/O port expander, and shift register U801 functions as a D/A converter to provide a
These devices are cascaded together on the serial bus so that data is shifted out of one device into another. Programming is performed using the SPI serial port of the microcontroller described in Section
3.3.1.The input to the internal shift register of these devices is the DATA (U800/U801) or SDI (U802) pin, and the output of the last shift register stage in U800 and U801 is the QS pin. Therefore, serial data on the Data line from the audio/logic board (J201, pin 14) is first shifted into U801, then U800, and then U802.
Data is clocked through the devices by the CLOCK signal (J201, pin 13) when the STROBE input (J201, pin 12) is high and latched when it goes low. Synthesizer IC U804 is also programmed by the SPI port. However, data does not pass through the other devices because it is controlled by a different STROBE signal (J201, pin 1).
3.11RECEIVER CIRCUIT DESCRIPTION (800/900 MHz MODELS)
NOTE: The receiver block diagram is in Figure
3.11.1 FRONT END FILTER
The receive signal is fed from the antenna switch circuit on the PA board to the receiver front end on the RF board. The signal is fed through a
3.11.2 RF AMPLIFIER (Q201)
RF amplifier Q201 improves and stabilizes receiver sensitivity and also recovers filter losses. A section of microstrip and C214 provide impedance matching on the input. CR203 protects the base- emitter junction of Q201 from damage caused by high level input signals.
The bias current of Q201 is fixed at a constant level by Q200. The collector current of Q201 flows through R207, and the voltage drop across that resistor (and therefore the current) is set by R205 and R206.
| February 2001 |
Part No. |