IBM ECS-320A Appendix E - Dynamic Memory Definitions

SERIAL INTERFACE DEVELOPERS GUIDE

Appendix E - Dynamic Memory Definitions

Note: The address (Adr) listed in the tables that follow refer to the RAM offset address inside

the Real Time Clock/NVM RAM part.

Factory Bit Fields

Adr Entry Name Mode Initialize 15 14 13 12 11 10 9876543210

32 Camera Short 0x0009

Mode R/W

Control

34 FPA Processor Short 0x0000

User Mode R/W

Control

36 Reserved Short 0x0000

R/W

38 Active Byte 0x00

Operational R/W

Mode

39 Active Byte 0x00

NUC R/W

Index

40 Reserved Short 0x0000

R/W

42 Auto NUC Switch Short 0x0200

Low Saturation R/W

Intensity Threshold

44 Auto NUC Switch Short 0x03E8

Low Saturation R/W

Count Threshold

46 Auto NUC Switch Short 0x3E00

High Saturation R/W

Intensity Threshold

48 Auto NUC Switch Short 0x03E8

High Saturation R/W

Count Threshold

Act Op Mod

Auto

Nuc

Sw

Act NucIndxReserved

CVid

0Out

En

CVid

1Out

En

SVid

Out

En

Pfv

Out

En

Reserved

Reserved

Auto

Rfsh

Tim

Auto

Rfsh

Tmp

Zn

Stat

En

Reserved PFV

Src

Sel

Dspl

Vid

Pol

Clr

Plt

YSel

Mstr

Sync

Mod

Clr

Bar

En Reserved

Res-

er-

ved

Reserved

Reserved

Auto NUC Switch Low Sa turation Count Threshold

Auto NUC Switch High Saturation Count Threshold

Auto NUC Switch Low Saturation Intensity ThresholdReserved

Auto NUC Switch High Satu ration Intensity ThresholdReserved

Atc

En

Rfsh

On

Boot

Rfsh

On

Sw

Res-

er-

ved

Rtcl

B

En

Rtcl

A

En

Camera Mode Control:

CVid0 Out En 0 – Composite Video 0 Output Disabled (Hi-Z);

1 – Composite Video 0 Output Enabled (Low Impedance Drive)

CVid1 Out En 0 – Composite Video 1 Output Disabled (Hi-Z);

1 – Composite Video 1 Output Enabled (Low Impedance Drive)

SVid Out En 0 – SVideo Output Disabled (Hi-Z);

1 – SVideo Output Enabled (Low Impedance Drive)

Pfv Out En 0 – Processed FPA Video Output Port Disabled (Hi-Z);

1 – Processed FPA Video Port Enabled (Low Impedance Drive)

Atc En 0 – Disable Ambient Temperature Compensation;

1 – Enable Ambient Temperature Compensation

Auto Nuc Sw 0 – Disable Auto NUC Switch;

1 – Enable Auto NUC Switch

Auto Rfsh Tim 0 – Disable Elapsed Time Based 1-Pt Refresh;

1 – Enable Elapsed Time Based 1-Pt Refresh

Auto Rfsh Tmp 0 – Disable Temperature Excursion Based 1-Pt Refresh;

51

Contents

Main Embeddable Camera Electronics System Page Page Page Page Page 1 Introduction 2 General Requirements 3 Camera Boot Sequence 3.1 Communication Configuration 3.2 Boot Messages 3.3 Software Upload 4 Interface Protocol 4.1 PC Master Information 4.2 Communications Configuration 5 Host Side Interface 5.1 Baud Rate 5.2 Function Subset 5.2.1 McbOpenCom 5.2.2 McbCloseCom 5.3 Lumitron Defined Commands 5.3.1 CMD_COPY_SFLASH_PAGE 5.3.2 CMD_PROG_SFLASH_FULL 5.3.3 CMD_PROG_SFLASH_PARTIAL 5.3.4 CMD_PROG_PRODUCT_ID 5.3.5 CMD_READ_PRODUCT_ID 5.3.6 CMD_PROG_STATIC_CFG 5.3.7 CMD_READ_STATIC_CFG 5.3.8 CMD_GET_CAMERA_TIME 5.3.9 CMD_SET_CAMERA_TIME 5.3.10 CMD_GET_NVM_DATA 5.3.11 CMD_SET_NVM_DATA 5.3.12 CMD_FOCUS_MOTOR_FAR 5.3.13 CMD_FOCUS_MOTOR_NEAR 5.3.14 CMD_IMAGE_GRAB 5.3.15 CMD_READ_UTILITY_MEMORY 5.3.16 CMD_NUC_FLASH_RAMP 5.3.17 CMD_NUC_FLASH_MEMORY 5.3.18 CMD_NUC_FLASH_TEST_PATTERN 5.3.19 CMD_TEC_DRV_ENABLE 5.3.20 CMD_TEC_TEMP_SELECT 5.3.21 CMD_CAL_FLAG_SERVO 5.3.22 CMD_CAL_FLAG_REFERENCE 5.3.23 CMD_ONE_PT_REFRESH 5.3.24 CMD_TWO_PT_NUC 5.3.25 CMD_LOAD_COLOR_PAL 5.3.26 CMD_LOAD_OVLY_PAL 5.3.27 CMD_PIN_CHECK 5.3.28 CMD_FAN_SPEED_OPERATION 5.3.29 CMD_GET_ADC_VALUES 5.3.30 CMD_ENABLE_RETICLE 5.3.31 CMD_RETICLE_POSITION 5.3.32 CMD_ONE_PT_UPDATE 5.3.33 CMD_WRITE_VID_ENC_REG 5.3.34 CMD_PERFORM_TEST 5.3.35 CMD_OVERLAY_REFRESH 5.3.36 CMD_FREEZE_IMAGE 5.3.37 CMD_DETECT_BAD_PIXELS 5.3.38 CMD_IRCON_LOAD_LUT 5.3.39 CMD_LOAD_RAD_PARAMS 5.3.40 CMD_RESET_PFV_COUNT 5.3.41 CMD_CLEAR_CONTINUE_FLAG 5.3.42 CMD_UNIFORMITY_TEST 5.3.44 CMD_ADV_DETECT_BAD_PIXELS 5.3.45 CMD_UPLOAD_NUC 5.3.46 CMD_DOWNLOAD_NUC 5.3.47 CMD_COMPILE_DEFECT_LISTS 5.3.48 CMD_RESTORE_FACTORY_DEFECTS 5.3.49 CMD_ENABLE_RANGE_RETICLE 5.3.50 CMD_INIT_NUC_TABLE 5.3.51 CMD_CAMERA_RECOVER 5.3.52 CMD_UPDATE_EXP_PORT 6 Camera Electronics Side Interface 6.1 DSP Data Memory 6.2 Global Configuration Structure (CAMERA_CONFIG) 6.2.1 CameraConfig.nvmData 6.2.2 CameraConfig.updateNVM 6.2.3 CameraConfig.continueFlag 6.2.4 CameraConfig.CmdsReceived 6.2.5 CameraConfig.camStats 6.2.6 CameraConfig.camErrors 6.2.7 CameraConfig.camTime 6.2.8 CameraConfig.expPort 6.2.9 CameraConfig.swVersion 6.2.10 CameraConfig.swBuild 6.2.11 CameraConfig.fpgaVersion[2] 6.2.12 CameraConfig.fpaSize 6.2.13 CameraConfig.agcLowIntensity 6.2.14 CameraConfig.agcHighIntensity 6.2.15 CameraConfig.actOpName[4] 6.2.18 CameraConfig.radSWInfo 6.2.19 CameraConfig.alarm 6.2.20 CameraConfig.calFlagRefs 6.2.21 CameraConfig.fpaInfo 6.2.22 CameraConfig.adcAFiltered[4] 6.2.23 CameraConfig.adcBFiltered[4] 6.2.24 CameraConfig.btnPanel 6.3 Dynamic Configuration Structure (NVM_GLOBAL_CFG) 6.3.1 nvmData.CamMode 6.3.2 nvmData.FpaMode 6.3.3 nvmData.ActMode 6.3.4 nvmData.AutoNucData 6.3.5 nvmData.AutoRfshTime 6.3.6 nvmData.AutoRfshTemp 6.3.7 nvmData.ActPal 6.3.9 nvmData.RtclXPos 6.3.10 nvmData.RadMode 6.3.11 nvmData.AgcMode 6.3.12 nvmData.ManualITT 6.3.13 nvmData.AgcLimits 6.3.14 nvmData.LinearMap 6.3.15 nvmData.AgcBinLimit 6.3.16 nvmData.ActZoneStat 6.3.17 nvmData.VidScaleTemps 6.3.18 nvmData.ImageParams 6.4 Process Code Detection (CAMERA_STATUS) 6.5 Progress Code Detection (CAMERA_STATUS) 6.6 Error Code Detection (CAMERA_ERRORS) 6.6.1 Configuration ID Error 6.6.2 FPGA Load 6.6.3 FPGA Test 6.6.4 Memory Test 6.6.5 Force 0 Test 6.6.6 Force 1 Test 6.6.7 Force Count Test 6.6.8 Force Count Coadd Test 6.6.9 Histogram Data Grab Test 6.6.10 NUC Gain and Offset Test 6.6.11 Video Encoder Test 6.7 Command Polling 6.8 Access to DSP Peripheral Registers (ArchIO) 6.9 Access to Xilinx FPGA Registers (FpgaIO) 6.9.1 FPA Processor Operational Control Register Low 6.9.2 FPA Processor Operational Control Register High 6.9.3 FPA Processor User Mode Control Register 6.9.4 ATC Offset Coefficient Register 6.10 Access to Serial Data Flash 7 Remote Calibration Process 7.1 One Point Refresh Calibration (Internal Flag): 7.2 One Point Refresh Calibration (External Flag): 7.3 One Point Update Calibration (Internal Flag): 7.4 One Point Update Calibration (External Flag): 7.5 Two Point Calibration (Internal Flags): 7.6 Two Point Calibration (External Flags): 7.7 Defective Pixel Detection 7.8 User Defined Defective Pixel Map 7.9 Upload NUC Table from Host 7.10 Download NUC Table to Host Page Appendix A - Camera Configuration Data Structures Page Page Appendix B - Xilinx Register/Data Structure Page Appendix C - Camera Command Enumerations Appendix D - Mapping of Serial Non-Volatile Memory Appendix E - Dynamic Memory Definitions Page Page Page Page Page Appendix F NUC Coefficient Format NUC Offset Coefficient (Odd Addresses) NUC Gain Coefficient (Even Addresses) Pixel Replace Address Offset