IBM 113, 8.3 Clock Output Function Control Registers

113
CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT
8.3 Clock Output Function Control Registers
The following two types of registers are used to control the clock output function.
• Timer clock select register 0 (TCL0)
• Port mode register 3 (PM3)
(1) Timer clock select register 0 (TCL0)
This register sets PCL output clock.
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TCL0 to 00H.
Figure 8-3. Timer Clock Select Register 0 Format
CLOE
7
0
6
00
4
TCL03
3210
FF40H
Address
TCL0
Symbol
TCL02TCL01 TCL00
5
00H
After
Reset
R/W
R/W
0
0
0
1
1
1
1
1
Other than above
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
TCL03TCL02 TCL01
fXX
fXX/2
fXX/22
fXX/23
fXX/24
fXX/25
fXX/26
fXX/27
Setting prohibited
MCS=1
fX (5.0 MHz)
fX/2 (2.5 MHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
MCS=0
fX/2 (2.5 MHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
PCL Output Clock Selection
CLOE
0
1
PCL Output Control
Output disable
Output enable
TCL00
1
0
1
0
1
0
1
0
Cautions 1. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
2. When rewriting TCL0 to other data, stop the clock operation beforehand.
3. Set 0 to bits 4 to 6.
Remarks 1. fXX : Main system clock frequency (fX or fX/2)
2. fX: Main system clock oscillation frequency
3. MCS : Oscillation mode selection register (OSMS) bit 0
4. Values in parentheses when operated at fX = 5.0 MHz.