IBM FIGURE (1/4)

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FIGURE (1/4)
Fig. No. Title Page
2-1 Pin Input/Output Circuit of List............................................................................................ 23
3-1 Memory Map (
µ PD78081) .................................................................................................. 25
3-2 Memory Map (
µ PD78082) .................................................................................................. 26
3-3 Memory Map (
µ PD78P083)................................................................................................ 27
3-4 Data Memory Addressing (
µ PD78081)............................................................................... 30
3-5 Data Memory Addressing (
µ PD78082)............................................................................... 31
3-6 Data Memory Addressing (
µ PD78P083) ............................................................................ 32
3-7 Program Counter Configuration ......................................................................................... 33
3-8 Program Status Word Configuration................................................................................... 33
3-9 Stack Pointer Configuration................................................................................................ 35
3-10 Data to be Saved to Stack Memory.................................................................................... 35
3-11 Data to be Reset from Stack Memory ................................................................................ 35
3-12 General Register Configuration .......................................................................................... 36
4-1 Port Types .......................................................................................................................... 53
4-2 P00 Block Diagram............................................................................................................. 56
4-3 P01 to P03 Block Diagram ................................................................................................. 56
4-4 P10 to P17 Block Diagram ................................................................................................. 57
4-5 P30 to P37 Block Diagram ................................................................................................. 58
4-6 P50 to P57 Block Diagram ................................................................................................. 59
4-7 P70 Block Diagram............................................................................................................. 60
4-8 P71 and P72 Block Diagram .............................................................................................. 61
4-9 P100 to P101 Block Diagram ............................................................................................. 62
4-10 Port Mode Register Format ................................................................................................ 65
4-11 Pull-Up Resistor Option Register Format ........................................................................... 66
5-1 Block Diagram of Clock Generator..................................................................................... 70
5-2 Processor Clock Control Register Format.......................................................................... 71
5-3 Oscillation Mode Selection Register Format ...................................................................... 72
5-4 Main System Clock Waveform due to Writing to OSMS.....................................................
5-5 External Circuit of Main System Clock Oscillator ............................................................... 73
5-6 Examples of Oscillator with Bad Connection (1/2) ............................................................. 74
5-7 CPU Clock Switching ......................................................................................................... 78
6-1 8-Bit Timer/Event Counters 5 and 6 Block Diagram........................................................... 82
6-2 Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit ................... 83
6-3 Timer Clock Select Register 5 Format................................................................................ 85
6-4 Timer Clock Select Register 6 Format................................................................................ 86
6-5 8-Bit Timer Mode Control Register 5 Format...................................................................... 87
6-6 8-Bit Timer Mode Control Register 6 Format...................................................................... 88
6-7 Port Mode Register 10 Format ........................................................................................... 89
6-8 8-Bit Timer Mode Control Register Settings for Interval Timer Operation.......................... 90
6-9 Interval Timer Operation Timings ....................................................................................... 91