IBM PD78081, PD78081(A), PD78082, PD78082(A), PD78083, PD78P081(A2), PD78P083, PD78P083(A), uPD78081, uPD78081(A), uPD78082, uPD78082(A), uPD78P081(A2), uPD78P083, uPD78P083(A)

CHAPTER 3 CPU ARCHITECTURE

15 0

Short Direct Memory

Effective Address 1111111

OP code

saddr-offset

[Description example]

MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H

Operation code 0 0 0 1 0 0 0 1 OP code

0 0 1 1 0 0 0 0 30H (saddr-offset)

0 1 0 1 0 0 0 0 50H (immediate data)

[Illustration]

When 8-bit immediate data is 20H to FFH, α = 0

When 8-bit immediate data is 00H to 1FH, α = 1

Contents

Main PD78083 SUBSERIES 8-BIT SINGLE-CHIP MICROCONTROLLER NOTES FOR CMOS DEVICES Page Page Regional Information Major Revision in This Edition The mark shows major revised points. PREFACE Page Page Development Tool Documents (Users Manuals) Page Page Page Page Page Page FIGURE (1/4) FIGURE (2/4) FIGURE (3/4) Page TABLE (1/2) TABLE (2/2) Page 1 CHAPTER 1 OUTLINE 1.1 Features 2 1.2 Applications Remark indicates ROM code suffix. 1.3 Ordering Information 3 1.4 Quality Grade Note Under planning Remark indicates ROM code suffix. 4 1.5 Pin Configuration (Top View) (1) Normal operating mode 42-pin plastic shrink DIP (600 mil) PD78081CU-, 78082CU-, 78P083CU, 78P083CU(A) 42-pin ceramic shrink DIP (with window) (600 mil) PD78P083DU 44-pin plastic QFP (10 10 mm) PD78081GB--3B4, 78081GB--3BS-MTX PD78082GB--3B4, 78082GB--3BS-MTX PD78P083GB-3B4, 78P083GB-3BS-MTX PD78081GB(A)--3B4, 78082GB(A)--3B4 6 Pin Identifications (2) PROM programming mode 42-pin plastic shrink DIP (600 mil) PD78P083CU, 78P083CU(A) 42-pin ceramic shrink DIP (with window) (600 mil) PD78P083DU 44-pin plastic QFP (10 10 mm) PD78P083GB-3B4, 78P083GB-3BS-MTX PD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX 9 1.6 78K/0 Series Development Note Under planning The following shows the 78K/0 Series products development. Subseries names are shown inside frames. The following table shows the differences among subseries functions. Note 10 bits timer: 1 channel 11 1.7 Block Diagram 12 1.8 Outline of Function 13 PD78081, 78082 and 78P083, the PD78081, 78082 and 78P083, the Table 1-1 Differences between the 1.9 Differences between the Page 15 CHAPTER 2 PIN FUNCTION 2.1 Pin Function List 2.1.1 Normal operating mode pins (1) Port pins (2) Pins other than port pins 2.1.2 PROM programming mode pins ( PD78P083 only) 17 2.2 Description of Pin Functions Page Page Page Page 22 Table 2-1. Type of Input/Output Circuit of Each Pin Figure 2-1. Pin Input/Output Circuit of List Page 25 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Spaces Figures 3-1 to 3-3 shows memory maps. Figure 3-1. Memory Map ( PD78081) Figure 3-2. Memory Map ( PD78082) Figure 3-3. Memory Map ( PD78P083) Page Page Figure 3-4. Data Memory Addressing ( PD78081) Figure 3-5. Data Memory Addressing ( PD78082) Figure 3-6. Data Memory Addressing ( PD78P083) 33 3.2 Processor Registers Page Page Page Page Table 3-2. Special-Function Register List (1/2) Page 40 3.3 Instruction Address Addressing Page Page Page 44 3.4 Operand Address Addressing Page Page Page Page Page Page Page Page 53 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions Table 4-1. Port Functions 55 4.2 Port Configuration Page Page Page Page Page Page Page 63 4.3 Port Function Control Registers Page Figure 4-10. Port Mode Register Format Caution Set 1 to the bits 0, 4 to 7 of PM0, bits 3 to 7 of PM7 and bits 2 to 7 of PM10. Page 67 4.4 Port Function Operations Page Page Figure 5-1. Block Diagram of Clock Generator 71 5.3 Clock Generator Control Register Page 73 5.4 System Clock Oscillator Page Page 76 5.5 Clock Generator Operations 77 5.6 Changing CPU Clock Settings Page 79 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 80 6.1 8-Bit Timer/Event Counters 5 and 6 Functions Page 82 6.2 8-Bit Timer/Event Counters 5 and 6 Configurations Figure 6-2. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit 84 6.3 8-Bit Timer/Event Counters 5 and 6 Control Registers Figure 6-3. Timer Clock Select Register 5 Format 3. TI5 : 8-bit timer register 5 input pin 3. TI6 : 8-bit timer register 6 input pin Page Page Page 90 6.4 8-Bit Timer/Event Counters 5 and 6 Operations Figure 6-9. Interval Timer Operation Timings Remarks 1. Interval time = (N + 1) t : N = 00H to FFH 2. n = 5, 6 Page Page Page Page Page Figure 6-14. PWM Output Operation Timing (Active high setting) Figure 6-15. PWM Output Operation Timings (CRn0 = 00H, active high setting) Figure 6-16. PWM Output Operation Timings (CRn0 = FFH, active high setting) Figure 6-17. PWM Output Operation Timings (CRn0 changing, active high setting) 100 6.5 Cautions on 8-Bit Timer/Event Counters 5 and 6 Page Page 103 CHAPTER 7 WATCHDOG TIMER 7.1 Watchdog Timer Functions Page 105 CHAPTER 7 WATCHDOG TIMER Control register 7.2 Watchdog Timer Configuration Page Figure 7-2. Timer Clock Select Register 2 Format 5. Values in parentheses when operated at fX = 5.0 MHz. 3. : Dont care Page 109 7.4 Watchdog Timer Operations Page Page 112 8.2 Clock Output Control Circuit Configuration Control register 113 8.3 Clock Output Function Control Registers Page 115 CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT 9.1 Buzzer Output Control Circuit Functions 9.2 Buzzer Output Control Circuit Configuration Page Figure 9-2. Timer Clock Select Register 2 Format 3. : dont care Page 119 CHAPTER 10 A/D CONVERTER 10.1 A/D Converter Functions 10.2 A/D Converter Configuration Figure 10-1. A/D Converter Block Diagram Page Page Figure 10-2. A/D Converter Mode Register Format Notes 1. Set so that the A/D conversion time is 19.1 s or more. 2. Setting prohibited because A/D conversion time is less than 19.1 Page Caution Set 0 to the bits 2 to 7. 126 10.4 A/D Converter Operations Page Page Page Page 131 10.5 A/D Converter Cautions Page Page Page 135 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 11.1 Serial Interface Channel 2 Functions Page f Figure 11-1. Serial Interface Channel 2 Block Diagram Note See Figure 11-2 for the baud rate generator configuration. CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Figure 11-2. Baud Rate Generator Block Diagram TPS0-TPS3 SCK CSCK ASCK/SCK2/P72 4 Page 140 11.3 Serial Interface Channel 2 Control Registers Figure 11-4. Asynchronous Serial Interface Mode Register Format Table 11-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode (2) 3-wire Serial I/O Mode (3) Asynchronous Serial Interface Mode Page Figure 11-6. Baud Rate Generator Control Register Format (1/2) Page Page Page 148 11.4 Serial Interface Channel 2 Operation Page Page Page Page (d) Baud rate generator control register (BRGC) (continued) Remark fSCK : 5-bit counter source clock k : Value set in MDL0 to MDL3 (0 k 14) Page Page Page Page Page Page Page Page Page Page When the 3-wire serial I/O mode is selected, 00H should be set in ASIM. (c) Baud rate generator control register (BRGC) (continued) Remark fSCK : 5-bit counter source clock k : Value set in MDL0 to MDL3 (0 k 14) Page Page Page 169 Page 171 CHAPTER 12 INTERRUPT FUNCTION 12.1 Interrupt Function Types 172 12.2 Interrupt Sources and Configuration Figure 12-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt (B) Internal maskable interrupt Page 175 12.3 Interrupt Function Control Registers Page Page Page Caution Set 0 to the bits 0 to 3. Figure 12-6. External Interrupt Mode Register 1 Format Caution Set 0 to the bits 2 to 7. Page 181 12.4 Interrupt Servicing Operations Figure 12-8. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment TMIF4 : Watchdog timer interrupt request flag Page Page CHAPTER 12 INTERRUPT FUNCTION Figure 12-11. Interrupt Request Acknowledge Processing Algorithm IE=1? Start IF=1? MK=0? PR=0? IE=1? ISP=1? Figure 12-12. Interrupt Request Acknowledge Timing (Minimum Time) f Remark 1 clock : (fCPU: CPU clock) 1 Page Table 12-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing Remarks 1. 2. 3. 4. Page Page Page Page 193 CHAPTER 13 STANDBY FUNCTION 13.1 Standby Function and Configuration CHAPTER 13 STANDBY FUNCTION m 195 13.2 Standby Function Operations Page Remark : Dont care Page Page Page 201 CHAPTER 14 RESET FUNCTION 14.1 Reset Function Figure 14-2. Timing of Reset Input by RESET Input Figure 14-3. Timing of Reset due to Watchdog Timer Overflow Figure 14-4. Timing of Reset Input in STOP Mode by RESET Input Page Page 205 CHAPTER 15 PD78P083 206 15.1 Memory Size Switching Register 207 15.2 PROM Programming Page 15.2.2 PROM write procedure Figure 15-2. Page Program Mode Flowchart Remark: G = Start address N = Last address of program Figure 15-3. Page Program Mode Timing Figure 15-4. Byte Program Mode Flowchart Remark: G = Start address N = Last address of program Figure 15-5. Byte Program Mode Timing Page 214 15.3 Erasure Procedure ( 15.4 Opaque Film Masking the Window ( PD78P083DU Only) 15.5 Screening of One-Time PROM Versions Page 216 16.1 Legends Used in Operation List Page 218 16.2 Operation List 2. When an area except the internal high-speed RAM area is accessed. 3. Only when rp = BC, DE or HL 4. Except r = A Page Page Page Page Page Page Page Page Page Page Page Page Figure A-1. Development Tool Configuration 233 A.1 Language Processing Software Note The DF78083 can be used commonly with all the RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0. SRA78K0 SCC78K0 234 A.2 PROM Programming Tools 235 A.3 Debugging Tools Remark EV-9200G-44s are sold in sets of five units. A.3.1 Hardware A.3.2 Software (1/3) SSM78K0 A.3.2 Software (2/3) SID78K0 Page 239 A.4 OS for IBM PC 240 A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator Based on EV-9200G-44 (1) Package drawing (in mm) 242 Based on EV-9200G-44 (2) Pad drawing (in mm) Page 244 B.1 Real-time OS SMX78K0- 245 B.2 Fuzzy Inference Development Support System Page 247 APPENDIX C REGISTER INDEX C.1 Register Index Page 249 APPENDIX D REVISION HISTORY Major revisions by edition and revised chapters are shown below. Page Facsimile Message Thank you for your kind support. From:

IBM - page 71

Models: PD78081 PD78081(A) PD78082 PD78082(A) PD78083 PD78P081(A2) PD78P083 PD78P083(A) uPD78081 uPD78081(A) uPD78082 uPD78082(A) uPD78P081(A2) uPD78P083 uPD78P083(A)