Icom IC-F3063T, IC-F3061T, IC-F3062S Power Supply Circuits Main Unit, PLL Circuit Main Unit

A portion of the each VCO output is applied to the PLL IC (IC1, pin 6) via the buffer amplifi ers (Q4, Q5) and the tunable BPF (D30, D31, L40, C170−C174).

5-3-2 PLL CIRCUIT (MAIN UNIT)

The PLL circuit provides stable oscillation of the transmit frequency and receive 1st LO frequency. The PLL output frequency is controlled by the divided ratio (N-data) from the CPU.

The buffer-amplified VCO output signals from the tunable BPF (D30, D31, L40, C170−C174) are applied to the PLL IC (IC1, pin 6). The applied signals are divided at the prescaler and programmable counter according to the “SSO” signal from the CPU (IC18, pin 10). The divided signal is phase-compared with

the reference frequency signal from the reference frequency oscillator (X1), at the phase detector.

The phase difference is output from pin 4 as a pulse type signal after being passed through the internal charge pump. The output signal is converted into the DC voltage (lock voltage) by passing through the loop filter (R7, R9, R12, C17, C18, C20). The lock voltage is applied to the variable capacitors (D1 and D2 of RX VCO1, D7 and D8 of RX VCO2, D11 and D12 of TX VCO) and locked to keep the VCO frequency constant.

If the oscillated signal drifts, its phase changes from that of the reference frequency, causing a lock voltage change to compensate for the drift in the VCO oscillating frequency.

• PLL CIRCUIT
RX VCO1 (155–174 MHz)						D14
					Buffer
						to transmitter circuit
					Q6
Q1, D1–D4			TX VCO
						D15
				Buffer
						to 1st mixer circuit
				Q4
RX VCO2 (136–155 MHz)			Q3, D10–D12
					Buffer
Q2, D5–D8					Q5
				PLL IC (IC1)
Loop	4	Charge	Programmable	Prescaler	6
filter		pump	divider		BPF

					14	SCK
	Phase	Divide		Shift register	15	SSO PLL control signals from the CPU (IC18)
		ratio
	detector				16
		adjustment				PLST
11
					10 15.3 MHz
			Reference				X1
PLL unlock signal			divider			reference frequency signal	15.3 MHz

to the CPU (IC18, pin 73)

5-4 POWER SUPPLY CIRCUITS (MAIN UNIT)

Voltage from the attached battery pack is routed to whole of the circuit in the transceiver via switches and regulators.

					1 1		"ATTERYTPACK
!TTACHED OPTIONAL UNITS					0OWERWSWITCH
			6##		(6
!& AMPLIFIER CONTROLLER
&2/.4 5.)4 1 1 $				)#
ETC
#050)#	#056			#056
%%02/- )#				REGURATOR
						#URRENT		2&25.)45
ETC
!TTACHED OPTIONAL UNITS						SENSOR		1 1 2
	6			6
$!CONVERTERS				REGURATOR
ETC	)#
0,,,)# )#			1 1 1		48 POWER AMPLIFIERS
	62%&	62%&
					2&25.)45141
"ASE BAND )# )#		REGURATOR
ETC

36

0,,,)# )#

		1
4RANSMITTERMCIRCUITS	46	46
		REGURATOR
	26
2ECEIVER CIRCUITS		26
		REGURATOR
		1

36		h3#v	
REGURATOR
1
	h4#v		
	h2#v		



#05 )#

6OLTAGETLINE

#ONTROLTSIGNAL

5 - 4