Intel 281809-003 manual Processor Upgrade, Second Level Cache, System Memory, Edo Dram

PROCESSOR UPGRADE

The Advanced/RH motherboard is manufactured with the 321-pin (socket 7) ZIF processor socket. Socket 7 provides a processor upgrade path that includes higher performance Pentium OverDrive processors than can be supported with socket 5. The motherboard is built to support uniplane CPUs. However, a manufacturing option allows the socket 7 design to support split voltage planes that can supply different voltages for a processor’s CPU core and for the I/O core. Installing a split plane CPU into a motherboard configured only for uniplane processor may cause damage to the CPU.

SECOND LEVEL CACHE

The Intel 82430HX PCIset supports a second level cache that uses high performance Synchronous Pipeline Burst SRAM. Asynchronous cache is not supported by the 82430HX controller. Pipeline Burst (PB) SRAM provides performance similar to expensive Synchronous Burst SRAMs for only a slight cost premium over slower performing asynchronous SRAMs.

As a manufacturing option, the Advanced/RH motherboard without onboard cache can be provided with a Card Edge Low Profile (CELP) version 2.1 socket that provides flexibility for second level cache options. The CELP socket can accommodate either a 256 KB or 512 KB cache module and is designed to work with modules that adhere to the COAST (Cache On A Stick) specification, version 2.1. The cache size is automatically detected and configured by the system BIOS for optimal performance. For a list of cache module suppliers or a copy of the COAST specification, contact your local Intel sales office or Intel authorized distributor.

SYSTEM MEMORY

The Advanced/RH motherboard provides six 72-pin SIMM sites for memory expansion. The sockets support 512 KB x 32 (2MB double sided SIMMs only), 1M x 32 (4 MB), 2M x 32 (8 MB), 4M x 32 (16 MB), 8M x 32 (32 MB), 16M x 32 (64MB), and 32M x 32 (128MB) single-sided or double-sided SIMM modules. Minimum memory size is 8 MB and maximum memory size, using four 32M x 32 SIMM modules, is 512 MB. Memory timing requires 70 ns fast page devices or, for optimum performance 60 ns EDO DRAM. 36-bit SIMM modules may be used for parity or ECC generation and checking.

The six sockets are arranged as Bank 0, Bank 1, and Bank 2. Each bank consists of two sockets and provides a 64/72-bit wide data path. Both SIMMs in a bank must be of the same memory size and type, although each bank may have different types of memory installed. It is even possible to have 70 ns Fast Page DRAM in one bank and 60 ns EDO DRAM in the other, in which case each bank is independently optimized for maximum performance. Any combination of the banks may be populated. There are no jumper settings required for the memory size or type, which is automatically detected by the system BIOS. The Advanced/RH motherboard supports only tin-lead SIMMs.

When banks 1 and 2 are populated at the same time, memory timing is modified from x333 to x444. This is due to loading on the address line shared by these two banks. In most applications the L2 cache will mask any performance degradation that is incurred. In addition, when using EDO Parity memory in an ECC configuration memory timing is changed from x222 to x333 to allow the chipset to perform Read Modify Writes.

EDO DRAM

Extended Data Out, or Hyper Page, DRAM is designed to improve the DRAM read performance. EDO DRAM holds the memory data valid until the next CAS# falling edge, unlike standard fast page mode DRAM which tri-states the memory data when CAS# negates to precharge for the next cycle. With EDO, the CAS# precharge overlaps the data valid time, allowing CAS# to negate earlier while still satisfying the memory data valid window time.

Advanced/RH Technical Product Specification ∙ Page 9