8xC251Tx Hardware Description
4
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
I/O Port 3. This is an 8 bit, bidir ectional I/O port with inte rnal pullups RXD
TXD
INT0#
INT1#
T0
T1
WR#
RD#/A16
PSEN# OProgram Store Enable. Read sign al ou t p ut to ex t e rna l memory.
Asserted for the address range specified by th e configuration byte
UCONFIG0, bits RD1:0.
RD# ORead. Read signal output to external memory. Asserted for the
address range spe cified by the conf iguration byte UCON FIG0, bits
RD1:0.
P3.7/A16
RST IReset. Reset input to the chip. Holding this pin high fo r 64 oscillator
periods while the oscil l ator is runn in g res et s th e devi ce. Th e por t p ins
are driven to their reset conditions when a voltage great er than VIH1
is applied, whether or not the oscillat or is running. Thi s signal has a
Schmitt trigger inpu t. Connecting the RST pin to VCC thro ugh a
capacitor provides power-on reset. Asserting RST whe n the chip is in
idle mode or powerdown mode returns the chip to normal operation.
RXD I/O Receive Serial Dat a . RX D sen d an d re cei ve s da ta i n se ria l I /O mode
0 and receives data in serial I/O modes 1, 2 and 3. P3.0
RXD1 I/O Receive Serial Data 1. RXD send and recei ves data in serial I /O
mode 0 and receiv es data in serial I/O modes 1, 2 and 3 f or the sec-
ond serial I/O por t.
P1.2/ECI
T1:0 ITimer 1:0 External Clock Inputs. When Timer 1:0 operates as a
counter, a falling edge on the T1:0 pin in crements the count . P3.5:4
T2 I/O Timer 2 Clock Input/Output. For Timer 2 capture mode, this signal
is the external clock input . For the clock-out mode , it is the timer 2
clock input.
P1.0
T2EX ITimer 2 External Input. In Timer 2 capture mode, a fal li ng edge ini-
tiates a capture of Timer 2 registers. In aut o-reload mode, a falling
edge causes the Timer 2 registers to be reloaded. In the up-down
counter mode, this signal determines the count direction:
•1=up
•0 = down.
P1.1
TXD OTransmit Serial Data. TXD outputs the shift clock in serial I/O mode
0 and transmits ser ial data in serial I/ O modes 1, 2 and 3 . P3.1
TXD1 OTransmit Serial Data 1. TXD outputs the shift clock in serial I/O
mode 0 and transmits se r ial data in serial I/O mode s 1 , 2 a nd 3 f or th e
second serial I/O port .
P1.3/CEX0
VCC PWR Supply Voltage. Connect this pin to the +5 supply voltage.
Table 2. 8xC251Tx Signal Descriptions (She et 2 of 3)
Signal
Name Type Description Alternate
Function
* The description s of A15:8/P2.7:0 and AD7:0/P0.7:0 are for non page mod e configuration. If configured in
page mode, Port 0 ca rries the lower a ddress bits (A7:0) and Port 2 carries the upper address bits (A15:8)
and the data (D7:0)