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8xC251Tx Hardware Description
Table 2. 8xC251Tx Signal Descriptions (Sheet 1 of 3)
Signal
Name Type Description Alternate
Function
A17 OAddress Line 17. Output to memory as the 18th external address bit
(A17) in extended bu s applications, d epending on the val ues of bits
RD0 and RD1 in confi guration byte UCO NFIG0 (see Chapte r 4,
"Device Configuration," of the 8xC251SA, 8xC251SB, 8xC251SP,
8xC251SQ Embedded Microcontroller Us er’s Manual (272795). See
also RD# and PSEN#.
P1.7/CEX4/
WCLK
A16 OAddress Line 16. See RD#. P3.7/RD#
A15:8* OAddress Lines. Upper addres s lines for the exte rnal bus. P2.7:0
A7:0 I/O Address/Data Lines. Multiplexed lowe r address lines and data lines
for external bus. P0/7:0
ALE OAddress Latch Enable. ALE signals the start of an external bus
cycle and indicate s t hat va li d addr es s i nfo rm ati on is av ai la ble on li n es
A15:8 and A7:0. An external latch can use ALE to demultiplex the
address from the ad dress/data bus.
CEX0
CEX1
CEX2
CEX3
CEX4
I/O Programmable Counter Array (PCA) in put/output pins. These are
input signals for the PC A capture mode and output si gnals for the
PCA compare mode and PCA PWM mode.
P1.3/TXD1
P1.4
P1.5
P1.6/WAIT#
P1.7/A17/
WCLK
EA# IExternal Access. Direct program accesses to on-chip or off-chip
code memory. For EA# = 0, all program me mory accesses are off
chip. For EA# = 1, all program memory accesses are on-c hip if the
address is within the range of the on-chip program memory; other-
wise the access is off-chip. The value of EA# is latche d at reset. For
devices without on-chip program memory, EA# must be strapped to
ground.
ECI IPCA External Clock Input. External clock input to the 16 bit PCA
timer. P1.2/RXD1
INT1:0# IExternal Interrupts 0 and 1. These inputs set IE1:0 in the TCON
register. If bits IT1:0 in the TCON regist er are set, units IE1:0 are set
by the falling edge on the INT1#/INT0#. If bits IT1:0 are clear, bits
IE1:0 are set by a low level on INTO1:0#.
P3.3:2
P0.7:0 I/O Port 0. This is an 8 bit, open drain, bidirectional I/O por t. AD7:0
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
I/O Port 1. This is an 8 bit, bidir ectional I/O port with inte rnal pullups. T2
T2EX
ECI/RXD1
CEX0/TXD1
CEX1
CEX2
CEX3/WAIT#
CEX4/A17/
WCLK
P2.7:0 I/O Port 2. This is an 8 bit, bidi rectional I/O port with in ternal pullups. A15:8
* The description s of A15:8/P2.7:0 and AD7:0/P0.7:0 are for non page mod e configuration. If configured in
page mode, Port 0 ca rries the lower a ddress bits (A7:0) and Port 2 carries the upper address bits (A15:8)
and the data (D7:0)