8xC251Tx Hardware Description
12
4.0 EXTENDED DATA FLOAT TIMING
The Extended Data Fl oat Timing feat ure seeks to provide a sol ution to use rs that may be using slower
memory devices. Essentially, this feature extends the TRHDZ1 AC timing specification to accommodate
slower memory devices which require a longer period of dead time between a data and address bus cycles.
This feature is co ntrolled by a bit in t he Configuration byte (UCONFIG1). Bit 3 of UCONFIG1 in the 8xC251Tx
is defined as EDF#. I n the 8xC251Sx, Bit 3 is defined as WSB. The implications of this change are discussed
below. Refer to Chapter 4 of the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller
User’s Manual (272795) for details of the device configuration for the 8xC251Sx. The information in that
chapter is valid for the 8xC251Tx with the exception of the change noted in this section.

4.1 Summary of the Extended Data Float Timing Cha nges

EDF# is used to determine whether th e Extended Data Float Timing is enabl ed. Table 12 shows the definition
of UCONFIG1 for the 8xC251Tx. Only bit 3 has be en redefined.
Refer to the 8xC251SA, 8x C251SB, 8xC251SP, 8xC251S Q Embedded Microc ontroller User’s M anual
(272795) for the AC timings specifications.
Table 12. UCONFIG1 bit definitions for the 8xC251Tx
Bit Number Bit
Mnemonic Function
7:5 -Reserved for Internal or Future Use.
Set these bits when p rogramming UCON FIG1
4INTR Interrupt Mode:
If this bit is set, interrupts push 4 bytes onto the stack (the 3 bytes of the PC
and PSW1). If this bit is cle ar, interrupts push the 2 lower b ytes of the PC
onto the stack.
3EDF# Extended Data Float Timings:
When cleared, the extende d da ta f loa t tim in gs are enabled. When set,
8xC251Sx compatible AC timings are enabled
2:1 WSB1:0# External Wait State B (Region 01:):
WSB1# WSB2#
0 0 Inserts 3 w ait states for region 01:
0 1 Inserts 2 w ait states for region 01:
1 0 Inserts 1 w ait state for region 0 1:
1 1 Zero wait s tates for region 01:
0EMAP EPROM Map:
For devices with 16 Kbytes of on-c hip code memory, clea r this bit to ma p the
upper half of the on -chip code memory to region 00: (da ta memory). Maps
FF:2000H-FF:3FFFH to 00:E000H -00:FFFFH. If this bit is set, mappi ng does
not occur and the addresses in the range 00:E000H-00:FFFFH access
external RAM.