30 Specification Update
HSD49. AVX Gather Instruction That Should Result in #DF May Cause Unexpected System Behavior
Problem: Due to this erratum, an execution of a 128-bit AVX gather instruction may fail to
generate a #DF (double fault) when expected. Instructions impacted by this erratum
are: VGATHERDPS, VGATHERDPD, VGATHERQPS, VGATHERQPD, VPGATHERDD,
VPGATHERDQ, VPGATHERQD, and VPGATHERQQ.
Implication: When this erratum occurs, an operation which should cause a #DF may result in
unexpected system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD50. Throttling and Refresh Rate Maybe be Incorrect After Exiting Package C-State
Problem: When the OLTM (Open Loop Thermal Management) feature is enabled, the DIMM
thermal status reported in DDR_THERM_PERDIMM_STATUS (MCHBAR Offset 588CH)
may be incorrect following an exit from Package C3 or deeper.
Implication: The incorrect DIMM thermal status may result in degraded performance from unneeded
memory throttling and excessive DIMM refresh rates.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD51. Processor May Livelock During On Demand Clock Modulation
Problem: The processor may livelock when (1) a processor thread has enabled on demand clock
modulation via bit 4 of the IA32_CLOCK_MODULATION MSR (19AH) and the clock
modulation duty cycle is set to 12.5% (02H in bits 3:0 of the same MSR), and (2) the
other processor thread does not have on demand clock modulation enabled and that
thread is executing a stream of instructions with the lock prefix that either split a
cacheline or access UC memory.
Implication: Program execution may stall on both threads of the core subject to this erratum.
Workaround: This erratum will not occur if clock modulation is enabled on all threads when using on
demand clock modulation or if the duty cycle programmed in the
IA32_CLOCK_MODULATION MSR is 18.75% or higher.
Status: For the steppings affected, see the Summary Table of Changes.
HSD52. IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI is Incorrectly Cleared by SMI
Problem: FREEZE_PERFMON_ON_PMI (bit 12) in the IA32_DEBUGCTL MSR (1D9H) is
erroneously cleared during delivery of an SMI (system-management interrupt).
Implication: As a result of this erratum, the performance monitoring counters will continue to count
after a PMI occurs in SMM (system-management Mode).
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.