36 Specification Update
Status: For the steppings affected, see the Summary Table of Changes.
HSD74. Performance Monitoring Events May Report Incorrect Number of Load Hits or Misses to LLC
Problem: The following performance monitor events should count the numbers of loads hitting or
missing LLC. However due to this erratum, The L3_hit related events may over count
and the L3_miss related events may undercount.
MEM_LOAD_RETIRED.L3_HIT (Event D1H, Umask 40H)
MEM_LOAD_RETIRED.L3_MISS (Event D1H, Umask 20H)
MEM_LOAD_L3_HIT_RETIRED. XSNP_NONE (Event D2H, Umask 08H)
MEM_LOAD_LLC_MISS_RETIRED. LOCAL_DRAM (Event D3H, Umask 01H)
Implication: The listed performance monitoring events may be inaccurate.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD75. Performance Monitoring Event INSTR_RETIRED.ALL May Generate Redundant PEBS Records For an Overflow
Problem: Due to this erratum, the performance monitoring feature PDIR (Precise Distribution of
Instructions Retired) for INSTR_RETIRED.ALL (Event C0H; Umask 01H) will generate
redundant PEBS (Precise Event Based Sample) records for a counter overflow. This can
occur if the lower 6 bits of the performance monitoring counter are not initialized or
reset to 0, in the PEBS counter reset field of the DS Buffer Management Area.
Implication: The above event count will under count on locked loads hitting the L2 cache.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD76. Locked Load Performance Monitoring Events May Under Count
Problem: The performance monitoring events MEM_TRANS_RETIRED.LOAD_LATENCY (Event
CDH; Umask 01H), MEM_LOAD_RETIRED.L2_HIT (Event D1H; Umask 02H), and
MEM_UOPS_RETIRED.LOCKED (Event DOH; Umask 20H) should count the number of
locked loads. Due to this erratum, these events may under count for locked
transactions that hit the L2 cache.
Implication: The above event count will under count on locked loads hitting the L2 cache.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD77. Graphics Processor Ratio And C-State Transitions May Cause a System Hang
Problem: If ratio or C-state changes involving the processor core and processor graphics occur at
the same time or while processor graphics are active, under certain internal conditions
the ratio change may not complete.
Implication: The system may hang during C-state or ratio changes.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.