46 Specification Update
The page fault (in #4) may report an incorrect error code and faulting linear address;
these would describe the read-modify-write instruction’s memory access instead of that
of the faulting instruction. (The address of the faulting instruction is reported correctly.)
Implication: The erratum makes it appear that the page fault resulted from an access that occurred
prior to the faulting instruction. Because the earlier access completed without faulting,
a page-fault handler may identify the page fault as transient (or spurious) and re-
execute the faulting instruction (e.g., by executing IRET). In such cases, the erratum
will not recur; the page fault on the later access will recur and will be reported
correctly. If the page-fault handler does not re-execute the faulting instruction, this
erratum may result in unpredictable system behavior. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD117. CATERR# Pin Assertion is Not Cleared on a Warm Reset
Problem: If the CATERR# pin is held asserted to indicate a fatal error, a subsequent warm reset
event will not cause the CATERR# pin to de-assert.
Implication: When this erratum occurs, platforms that monitor the CATERR# pin may be unable to
detect a fatal error after a warm reset or may incorrectly respond to a CATERR# pin
assertion although an error may not have occurred subsequent to the warm reset
event.
Workaround: The CATERR# pin can be de-asserted by a cold reset event.
Status: For the steppings affected, see the Summary Table of Changes.
HSD118. Uncorrectable Machine Check Error During Core C6 Entry May Not be Signaled
Problem: Machine Check exceptions occurring during core C6 entry may be ignored.
Implication: When this erratum occurs, incorrect state may be saved during core C6 entry and
subsequently restored during core C6 exit resulting in unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
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