Intel BX80646G3420, BX80646I54430, BX80646I54440, BX80646I54570, BX80646I54570S, BX80646I54670, BX80646I54670K, BX80646I74770, BX80646I74770K, BX80646I74770S, BX80646I74771, BXF80646I54670K, CM8064601465703, CM8064601465902, CM8064601466003, CM8064601466200, CM8064601466203 Nomenclature

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Specification Update 7

Nomenclature

Errata are design defects or errors. These may cause the processor behavior to

deviate from published specifications. Hardware and software designed to be used with

any given stepping must assume that all errata documented for that stepping are

present on all devices.

S-Spec Number is a five-digit code used to identify products. Products are

differentiated by their unique characteristics such as, core speed, L2 cache size,

package type, etc. as described in the processor identification information table. Read

all notes associated with each S-Spec number.

Specification Changes are modifications to the current published specifications.

These changes will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further

highlight a specification’s impact to a complex design situation. These clarifications will

be incorporated in any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current

published specifications. These will be incorporated in any new release of the

specification.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a

particular stepping is no longer commercially available. Under these circumstances,

errata removed from the specification update are archived and available upon request.

Specification changes, specification clarifications and documentation changes are

removed from the specification update when the appropriate changes are made to the

appropriate product specification or user documentation (datasheets, manuals, and so

on).

Contents

Main Page Contents Page Revision History Preface ACPI Specifications www.acpi.info Related Documents Affected Documents Nomenclature Summary Tables of Changes Codes Used in Summary Tables Errata (Sheet 1 of 5) Errata (Sheet 2 of 5) Errata (Sheet 3 of 5) Errata (Sheet 4 of 5) Specification Changes Specification Clarifications Documentation Changes Errata (Sheet 5 of 5) Identification Information Component Identification using Programming Interface The processor stepping can be identified by the following register contents. Notes: Table 1. Desktop 4th Generation Intel Core Processor Family Component Identification Component Marking Information Table 2. Desktop Processor Identification (Sheet 1 of 2) Table 2. Desktop Processor Identification (Sheet 2 of 2) Errata HSD1. LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode HSD2. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change HSD3. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error Page HSD8. FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM HSD9. APIC Error Received Illegal Vector May be Lost Page HSD15. Processor May Fail to Acknowledge a TLP Request HSD16. Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered HSD18. PCIe* Controller May Incorrectly Log Errors on Transition to RxL0s HSD19. Unused PCIe* Lanes May Report Correctable Errors HSD21. PCIe Root Port May Not Initiate Link Speed Change HSD22. Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected Page HSD29. Performance Monitor Counters May Produce Incorrect Results HSD30. Performance Monitor UOPS_EXECUTED Event May Undercount HSD31. MSR_PERF_STATUS May Report an Incorrect Core Voltage HSD32. PCIe* Atomic Transactions From Two or More PCIe Controllers May Cause Starvation HSD34. An AVX Gather Instruction That Causes an EPT Violation May Not Update Previous Elements HSD35. PLATFORM_POWER_LIMIT MSR Not Visible HSD36. LPDDR Memory May Report Incorrect Temperature HSD37. PCIe* Host Bridge DID May Be Incorrect HSD38. TSC May be Incorrect After a Deep C-State Exit Page HSD44. Display May Flicker When Package C-States Are Enabled HSD45. Certain Combinations of AVX Instructions May Cause Unpredictable System Behavior HSD46. Processor May Incorrectly Estimate Peak Power Delivery Requirements HSD47. IA32_PERF_CTL MSR is Incorrectly Reset HSD48. Processor May Hang During a Function Level Reset of the Display HSD49. AVX Gather Instruction That Should Result in #DF May Cause Unexpected System Behavior HSD50. Throttling and Refresh Rate Maybe be Incorrect After Exiting Package C-State HSD51. Processor May Livelock During On Demand Clock Modulation HSD52. IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI is Incorrectly Cleared by SMI HSD53. The From-IP for Branch Tracing May be Incorrect HSD54. TM1 Throttling May Continue indefinitely HSD55. Internal Parity Errors May Incorrectly Report Overflow in The IA32_MCi_STATUS MSR HSD57. Processor May Run at Incorrect P-State Page HSD62. Some Performance Monitor Event Counts May be Inaccurate During SMT Mode HSD63. Timed MWAIT May Use Deadline of a Previous Execution HSD64. The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging HSD66. A PCIe* LTR Update Message May Cause The Processor to Hang HSD67. GETSEC Does Not Report Support For S-CRTM HSD68. EPT Violations May Report Bits 11:0 of Guest Linear Address Incorrectly HSD69. APIC Timer Might Not Signal an Interrupt While in TSC-Deadline Mode HSD71. Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be Observed HSD72. VT-d Hardware May Perform STRP And SIRTP Operations on a Package C7 Exit HSD73. General-Purpose Performance Counters Can Unexpectedly Increment HSD74. Performance Monitoring Events May Report Incorrect Number of Load Hits or Misses to LLC HSD76. Locked Load Performance Monitoring Events May Under Count HSD77. Graphics Processor Ratio And C-State Transitions May Cause a System Hang HSD78. Certain Performance Monitoring Events May Over Count Software Demand Loads HSD79. Accessing Nonexistent Uncore Performance Monitoring MSRs May Not Signal a #GP HSD80. Call Stack Profiling May Produce Extra Call Records HSD81. Warm Reset May Fail or Lead to Incorrect Power Regulation Page Page Page Page Page Page HSD109. Processor Energy Policy Selection May Not Work as Expected HSD110. A PEBS Record May Contain Processor State for an Unexpected Instruction HSD111. MSR_PP1_ENERGY_STATUS Reports Incorrect Energy Data HSD112. x87 FPU DP May be Incorrect After Instructions That Save FP State to Memory Page HSD117. CATERR# Pin Assertion is Not Cleared on a Warm Reset HSD118. Uncorrectable Machine Check Error During Core C6 Entry May Not be Signaled Specification Changes Specification Clarifications Documentation Changes HSD1. On-Demand Clock Modulation Feature Clarification