Intel IQ80333 manual 3.4Memory Subsystem, 3.4.1DDR SDRAM, 3.4.1.1Battery Backup

Intel® IQ80333 I/O Processor

Hardware Reference Section

3.4Memory Subsystem

The Memory Controller of 80333 controls the DDR SDRAM memory subsystem. It features pro- grammable chip selects and support for error correction codes (ECC). The memory controller can be configured for DDR SDRAM at 333 MHz and DDR-II at 400 MHz. The memory controller supports pipelined access and arbitration control to maximize performance. The memory controller interface configuration support includes Unbuffered DIMMs, Registered DIMMs, and discrete

DDR SDRAM devices.

This IQ80333 has DDR-II at 400 MHz DIMM on the board. The memory subsystem of the evaluation board consists of the SDRAM as well as the Flash memory subsystems.

3.4.1DDR SDRAM

The DDR SDRAM interface consists of a 64-bit wide data path to support up to 3.2 Gbytes/sec throughput. An 8-bit Error Correction Code (ECC) is stored into the DDRII SDRAM array along with the data and is checked when the data is read.

The IQ80333 features on board registered DDRII 400 MHz SDRAM, arranged 512 Mbit x16 in density (256 MB), and with ECC.

3.4.1.1Battery Backup

Battery backup is provided to save any information in DDR during a power failure. The evaluation board contains a 4 V Li-ion battery, a charging circuit and a regulator circuit.

DDRII technology provides enabling data preservation through the self-refresh command. When the processor receives an active Primary PCI-X reset, the self-refresh command issues, driving SCKE signals low. Upon seeing this condition, the board logic circuit holds SCKE low before the processor loses power. Batteries maintain power to DDRII and logic, to ensure self-refresh mode. When the circuit detects PRST# returning to inactive state, the circuit releases the hold on SCKE. Removing the battery can disable the battery circuit. When the battery remains in the platform when it is de-powered and/or removed from the chassis, the battery maintains DDRII for about four hours. Once power is reapplied, the battery is fully charged.

The CPLD contains information in regards to the battery status. Please see Section 3.6.7, “Battery Status” on page 34 for more details.

28 Customer Reference Board Manual