Kane Industries C6713CPU 3 Memory Maps and Description of the PLD Registers

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ARDWARE

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EFERENCE

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UIDE

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C6713CPU

Date : 28 November 2005

Doc. no. : C6713CPU_HRG

Iss./Rev : 1.1

Page : 20

3 Memory Maps and Description of the PLD Registers

3.1 TMS320C6713 Memory Map

The memory map of the TMS320C6713 is divided into several sections:

• internal memory

• DSP peripherals

• EMIF CE spaces CE0 .. CE3

The external devices are located at different CE (Chip Enable) spaces. The EMIF bus timing of

each CE space can be individually set up. The complete memory map is shown in Table 1. For a

more detailed memory map of the DSP please refer to [4].

address range (hex) size (bytes) Description

0000 0000 - 0002 FFFF 192KB Internal RAM

0003 0000 - 0003 FFFF 64KB Internal RAM/Cache

0004 0000 - 017F FFFF 24MB - 256KB Reserved

0180 0000 - 3C1F FFFF 938MB DSP peripherals

3C20 0000 - 7FFF FFFF 1GB + 62MB Reserved

8000 0000 - 8FFF FFFF 256MB (usable: 128MB ) EMIF CE0

9000 0000 - 9FFF FFFF 256MB (usable: 128MB ) EMIF CE1

A000 0000 – AFFF FFFF 256MB (usable: 128MB ) EMIF CE2

B000 0000 – BFFF FFFF 256MB (usable: 128MB ) EMIF CE3

C000 0000 – FFFF FFFF 1GB Reserved

Table 1: Memory map of the processor

Contents

Main Hardware Reference Guide micro-line C6713CPU High performance DSP / FPGA board Page Page Page Page C6713CPU 1 Preface 1.1 Document Organization 1.2 Documentation Overview 1.3 Notational conventions C6713CPU 1.4 Trademarks Page 2 Hardware Overview Page Page 2.2 Connectors 2.3 Interfaces and Hardware Components C6713CPU Page 2.4 Status LED's 2.5 DSP peripherals Page Page Page 3 Memory Maps and Description of the PLD Registers 3.1 TMS320C6713 Memory Map 3.2 C6713CPU Address Map 3.3 Internal fast SRAM 3.4 DSP Peripherals 3.5 External SDRAM 3.7 Endianness 3.8 EMIF Configuration 3.9 Description of the PLD Board Registers 3.10 Description of the PLD Registers Page Page Page Page 4 Boot Process and Default Setup of the C6713CPU 5 Using the Flash File System 6 Description of the micro-line Board Connectors Table 11: Pinout of the micro-line connectors 6.3 Pinout Tables of the micro-line Page Page 6.4 Pinout of the JTAG Connector FPGA J TAG connec tor DSP JTAG connecto r (fits TI emulator POD) top view 6.5 Function of the micro-line Connector Pins Page Page Page Page Page Page Page 7 Environment 7.1 Minimum Connections Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 45 D standard PC RS-232 connector Sub-D 9pin socket; fits directly into a PC front view Figure 9: Connecting the serial interface (RS-232) to a PC 7.2 Changing the Board Configuration Page 7.3 Signal Levels and Loads 7.4 Supply Voltage 7.5 Power Consumption 7.6 Reset Timing 7.7 Ambient Temperature 7.9 Dimensions of the Board Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 51 Figure 13: Complete micro-line footprint 7.10 Spare micro-line Connectors 8 List of abbreviations used in this document 9 Literature references