Kane Industries C6713CPU

ARDWARE

EFERENCE

UIDE

MICRO

LINE

C6713CPU

Date : 28 November 2005

Doc. no. : C6713CPU_HRG

Iss./Rev : 1.1

Page : 34

shared with Signal

interface signal

micro-line® connector

AXR0[7] FSR1 E14

AXR0[6] CLKR1 E12

AXR0[5]

McBSP

DX1 E11

AXR0[4] TOUT1 E29

AXR0[3] TINP0 E18

AXR0[2]

Timer

TOUT0 E28

AXR0[1] DX0 E21

AXR0[0] DR0 E20

ACLKR0 CLKR0 E22

AHCLKR0 CLKS0 E19

AFSR0 FSR0 E24

ACLKX0

McBSP

CLKX0 E23

AHCLKX0 Timer TINP1 E17

AFSX0 FSX0 E25

AMUTE0

McBSP

CLKX1 E13

AMUTEIN0 GPIO,

interrupt

GP5,

EXT_INT5

D18

AXR1[7] HD1 BB2

AXR1[6] /HDS1 BB23

AXR1[5] /HDS2 BB24

AXR1[4] HD0 BB1

AXR1[3] HCNTL0 BB18

AXR1[2] /HCS BB22

AXR1[1] HCNTL1 BB19

AXR1[0] HR/W BB21

ACLKR1 /HRDY BB25

AHCLKR1 HD6 BB7

AFSR1 HHWIL BB17

ACLKX1 /HAS BB20

AHCLKX1 HD5 BB6

AFSX1 HD2 BB3

AMUTE1

HPI

HD3 BB4

AMUTEIN1 GPIO,

interrupt

GP4,

EXT_INT4

D17

Table 15: Pinout summary and signal routing for the McASP interfaces

Contents

Main Hardware Reference Guide micro-line C6713CPU High performance DSP / FPGA board Page Page Page Page C6713CPU 1 Preface 1.1 Document Organization 1.2 Documentation Overview 1.3 Notational conventions C6713CPU 1.4 Trademarks Page 2 Hardware Overview Page Page 2.2 Connectors 2.3 Interfaces and Hardware Components C6713CPU Page 2.4 Status LED's 2.5 DSP peripherals Page Page Page 3 Memory Maps and Description of the PLD Registers 3.1 TMS320C6713 Memory Map 3.2 C6713CPU Address Map 3.3 Internal fast SRAM 3.4 DSP Peripherals 3.5 External SDRAM 3.7 Endianness 3.8 EMIF Configuration 3.9 Description of the PLD Board Registers 3.10 Description of the PLD Registers Page Page Page Page 4 Boot Process and Default Setup of the C6713CPU 5 Using the Flash File System 6 Description of the micro-line Board Connectors Table 11: Pinout of the micro-line connectors 6.3 Pinout Tables of the micro-line Page Page 6.4 Pinout of the JTAG Connector FPGA J TAG connec tor DSP JTAG connecto r (fits TI emulator POD) top view 6.5 Function of the micro-line Connector Pins Page Page Page Page Page Page Page 7 Environment 7.1 Minimum Connections Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 45 D standard PC RS-232 connector Sub-D 9pin socket; fits directly into a PC front view Figure 9: Connecting the serial interface (RS-232) to a PC 7.2 Changing the Board Configuration Page 7.3 Signal Levels and Loads 7.4 Supply Voltage 7.5 Power Consumption 7.6 Reset Timing 7.7 Ambient Temperature 7.9 Dimensions of the Board Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 51 Figure 13: Complete micro-line footprint 7.10 Spare micro-line Connectors 8 List of abbreviations used in this document 9 Literature references