Kane Industries C6713CPU 5 Using the Flash File System

H

ARDWARE

R

EFERENCE

G

UIDE

MICRO

-

LINE

®

C6713CPU

Date : 28 November 2005

Doc. no. : C6713CPU_HRG

Iss./Rev : 1.1

Page : 30

5 Using the Flash File System

The Flash File System of the C6713CPU consists of three parts:

• A target-resident boot loader which initializes the C6713CPU at startup, looks for

commands on the RS-232 interface and then either loads auto-boot FPGA(s) / application

or loads a Flash File System command executable over RS-232.

• DSP-side executables which perform the desired function

• PC-side utilities that connect to the C6713CPU, upload the DSP-side executables and

perform the desired function.

The Flash File System supports storage and boot sequence management for both, FPGA code

and DSP applications.

For correct operation of the Flash File System, it is recommended that the CTS-reset feature is

enabled in the PLD, see chapter 3.10.4 for details. This allows the Flash File System to interrupt

the currently running program and to connect to the C6713CPU. If the CTS-reset feature is

disabled, the C6713CPU must be reset manually.

A detailed description of the Flash File System is given in [24]

Contents

Main Hardware Reference Guide micro-line C6713CPU High performance DSP / FPGA board Page Page Page Page C6713CPU 1 Preface 1.1 Document Organization 1.2 Documentation Overview 1.3 Notational conventions C6713CPU 1.4 Trademarks Page 2 Hardware Overview Page Page 2.2 Connectors 2.3 Interfaces and Hardware Components C6713CPU Page 2.4 Status LED's 2.5 DSP peripherals Page Page Page 3 Memory Maps and Description of the PLD Registers 3.1 TMS320C6713 Memory Map 3.2 C6713CPU Address Map 3.3 Internal fast SRAM 3.4 DSP Peripherals 3.5 External SDRAM 3.7 Endianness 3.8 EMIF Configuration 3.9 Description of the PLD Board Registers 3.10 Description of the PLD Registers Page Page Page Page 4 Boot Process and Default Setup of the C6713CPU 5 Using the Flash File System 6 Description of the micro-line Board Connectors Table 11: Pinout of the micro-line connectors 6.3 Pinout Tables of the micro-line Page Page 6.4 Pinout of the JTAG Connector FPGA J TAG connec tor DSP JTAG connecto r (fits TI emulator POD) top view 6.5 Function of the micro-line Connector Pins Page Page Page Page Page Page Page 7 Environment 7.1 Minimum Connections Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 45 D standard PC RS-232 connector Sub-D 9pin socket; fits directly into a PC front view Figure 9: Connecting the serial interface (RS-232) to a PC 7.2 Changing the Board Configuration Page 7.3 Signal Levels and Loads 7.4 Supply Voltage 7.5 Power Consumption 7.6 Reset Timing 7.7 Ambient Temperature 7.9 Dimensions of the Board Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 51 Figure 13: Complete micro-line footprint 7.10 Spare micro-line Connectors 8 List of abbreviations used in this document 9 Literature references