Kane Industries C6713CPU

ARDWARE

EFERENCE

UIDE

MICRO

LINE

C6713CPU

Date : 28 November 2005

Doc. no. : C6713CPU_HRG

Iss./Rev : 1.1

Page : 5

List of Tables

Table 1: Memory map of the processor...........................................................................................20

Table 2: Memory map of the C6713CPU........................................................................................ 21

Table 3: default initialization values for the FPGA related CE space registers............................... 23

Table 4: CE2 default configuration.................................................................................................. 23

Table 5: CE3 default configuration.................................................................................................. 23

Table 6: PLD and UART registers of the C6713CPU......................................................................24

Table 7: PLD register quick reference.............................................................................................24

Table 8: Version register encoding..................................................................................................28

Table 9: Default clock and EMIF settings of the C6713CPU...........................................................29

Table 10: Connector overview.........................................................................................................32

Table 11: Pinout of the micro-line® connectors............................................................................... 32

Table 12: Pinout summary for the McBSP interfaces......................................................................33

Table 13: Pinout summary for the timers ........................................................................................33

Table 14: Pinout summary for the I2C interfaces.............................................................................33

Table 15: Pinout summary and signal routing for the McASP interfaces........................................ 34

Table 16: Pinout of the JTAG connector......................................................................................... 35

Table 17: Factory default configuration summary........................................................................... 46

Table 18: Voltage limits for the C6713CPU.....................................................................................49

Table 19: Power consumption of the C6713CPU............................................................................49

Table 20: Reset timing ....................................................................................................................49

List of Figures

Figure 1: Block diagram of the C6713CPU..................................................................................... 10

Figure 2: Top side of the C6713CPU.............................................................................................. 11

Figure 3: Bottom side of the C6713CPU......................................................................................... 11

Figure 4: FPGA connections overview............................................................................................ 13

Figure 5: Data representation in memory in little endian configuration........................................... 22

Figure 6: Connector locations .........................................................................................................31

Figure 7: JTAG adapter for the C6713CPU ....................................................................................35

Figure 8: Supplying the C6713CPU with power.............................................................................. 44

Figure 9: Connecting the serial interface (RS-232) to a PC............................................................ 45

Figure 10: Location of configuration elements (top side) ................................................................46

Figure 11: Location of configuration elements (bottom side) ..........................................................47

Figure 12: Dimensions of the C6713CPU (in millimeters)...............................................................50

Figure 13: Complete micro-line® footprint........................................................................................51

Figure 14: C6713CPU connector pins.............................................................................................52