Kane Industries C6713CPU , 7.9 Dimensions of the Board

H

ARDWARE

R

EFERENCE

G

UIDE

MICRO

-

LINE

®

C6713CPU

Date : 28 November 2005

Doc. no. : C6713CPU_HRG

Iss./Rev : 1.1

Page : 50

7.9 Dimensions of the Board

Figure 12 shows the dimensions of the C6713CPU. When the C6713CPU is stacked with other

modules, board spacing is 14mm.

C9

78.74

90.17

97.54

58.42

60.96

67.06

2.54

2.54

1,5

1,5

6,0

5,0

3,5

maximum heigh of components

Figure 12: Dimensions of the C6713CPU (in millimeters)

In case of a customized carrier design, it is recommended to reserve some more space additionally

to the existing micro-line® connectors of the C6713CPU. This space does not necessarily need to

be mounted with connectors. It is only recommended not to place components into this region. This

allows to mount micro-line® peripheral boards and/or future micro-line® processor boards in the

same socket. The full micro-line footprint is listed below. Recommended keep-out areas are

connector rows A, B, BB, C, D, E for CPU boards and A, B, BB, C, D, E, EGND 1..4, P, X1..X10 for

peripheral boards. Rows EE, 1394-1, 1394-2, EGND5 and X11..16 are very unlikely to be used

and can therefore be used for placing components.

Contents

Main Hardware Reference Guide micro-line C6713CPU High performance DSP / FPGA board Page Page Page Page C6713CPU 1 Preface 1.1 Document Organization 1.2 Documentation Overview 1.3 Notational conventions C6713CPU 1.4 Trademarks Page 2 Hardware Overview Page Page 2.2 Connectors 2.3 Interfaces and Hardware Components C6713CPU Page 2.4 Status LED's 2.5 DSP peripherals Page Page Page 3 Memory Maps and Description of the PLD Registers 3.1 TMS320C6713 Memory Map 3.2 C6713CPU Address Map 3.3 Internal fast SRAM 3.4 DSP Peripherals 3.5 External SDRAM 3.7 Endianness 3.8 EMIF Configuration 3.9 Description of the PLD Board Registers 3.10 Description of the PLD Registers Page Page Page Page 4 Boot Process and Default Setup of the C6713CPU 5 Using the Flash File System 6 Description of the micro-line Board Connectors Table 11: Pinout of the micro-line connectors 6.3 Pinout Tables of the micro-line Page Page 6.4 Pinout of the JTAG Connector FPGA J TAG connec tor DSP JTAG connecto r (fits TI emulator POD) top view 6.5 Function of the micro-line Connector Pins Page Page Page Page Page Page Page 7 Environment 7.1 Minimum Connections Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 45 D standard PC RS-232 connector Sub-D 9pin socket; fits directly into a PC front view Figure 9: Connecting the serial interface (RS-232) to a PC 7.2 Changing the Board Configuration Page 7.3 Signal Levels and Loads 7.4 Supply Voltage 7.5 Power Consumption 7.6 Reset Timing 7.7 Ambient Temperature 7.9 Dimensions of the Board Date : 28 November 2005 Doc. no. : C6713CPU_HRG Iss./Rev : 1.1 Page : 51 Figure 13: Complete micro-line footprint 7.10 Spare micro-line Connectors 8 List of abbreviations used in this document 9 Literature references