H
ARDWARE
R
EFERENCE
G
UIDE
MICRO
-
LINE
®
C6713CPU
Date : 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 32
6.2 Connector Overview
Table 10 gives an overview about usage of the micro-line® connectors, including the 'classic' usage
as peripheral interface as used with previous CPU boards. The classic peripheral interface is
implemented in the micro-line® busmaster BSP which is described in [21].
Connector Default micro-line® bus usage
A DSP data lines D[31:0]
B DSP address lines A[23:0]; digital signal ground
BB DSP host port interface
D Power supply, control signals for peripheral boards, RS-232 interface
E DSP peripherals
Table 10: Connector overview
6.3 Pinout Tables of the micro-line®
Connector On the C6713CPU, some signals have fixed functions, others (marked with "(FPGA)"), can be
used individually by a board support package, such as [21] or by a customized FPGA design. A
detailed signal description can be found in chapter 6.5.
Connector Pin
No. A B BB D E
Pin
No.
1 (FPGA) (FPGA) HD0 (I/O/Z) Power GND (I) (FPGA) 1
2 (FPGA) (FPGA) HD1 (I/O/Z) Power GND (I) (FPGA) 2
3 (FPGA) (FPGA) HD2
,
(I/O/Z) Power GND (I) (FPGA) 3
4 (FPGA) (FPGA) HD3
,
(I/O/Z) Power GND (I) (FPGA) 4
5 (FPGA) (FPGA) HD4
,
(I/O/Z) +3.3V (I) (FPGA) 5
6 (FPGA) (FPGA) HD5
,
(I/O/Z) +3.3V (I) (FPGA) 6
7 (FPGA) (FPGA) HD6
(I/O/Z) /RESETIN (I) (FPGA) 7
8 (FPGA) (FPGA) HD7
(I/O/Z) /RESETOUT (O) (FPGA) 8
9 (FPGA) (FPGA) HD8
(I/O/Z) RESETOUT (O) (FPGA) 9
10 (FPGA) (FPGA) HD9 (I/O/Z) (FPGA) DR1 (I) SDA1 (I/O/Z) 10
11 (FPGA) (FPGA) HD10
(I/O/Z) (FPGA) DX1 (O/Z) AXR0[5] (I/O/Z) 11
12 (FPGA) (FPGA) HD11
(I/O/Z) (FPGA) CLKR1 (I/O/Z) AXR0[6] (I/O/Z) 12
13 (FPGA) (FPGA) HD12
(I/O/Z) (FPGA) CLKX1 (I/O/Z) AMUTE0 (O/Z) 13
14 (FPGA) (FPGA) HD13
(I/O/Z) (FPGA) FSR1 (I/O/ Z) AXR0[7] (I/O/Z) 14
15 (FPGA) (FPGA) HD14
(I/O/Z) (FPGA) FSX1 (I/O/Z) 15
16 (FPGA) (FPGA) HD15
(I/O/Z) (FPGA) CLKS1 (I) SCL1 (I/O/Z) 16
17 (FPGA) (FPGA) HHWIL (I) (FPGA) / INT4 (I) TINP1 (I) AHCLKX0 (I/O/Z) 17
18 (FPGA) (FPGA) HCNTL0 (I) (FPGA) / INT5 (I) TINP0 (I) AXR0[3] (I/O/Z) 18
19 (FPGA) (FPGA) HCNTL1 (I) (FPGA) CLKS0 (I) AHCLKR0 (I/O/Z) 19
20 (FPGA) (FPGA) /HAS (I) (FPGA) DR0 (I) AXR0[0] (I/O/Z) 20
21 (FPGA) (FPGA) (FPGA) / HR/W (I) (FPGA ) DX0 (O/Z) AXR0[1] (I/O/Z) 21
22 (FPGA) (FPGA) (FPGA) / /HCS (I) (FPGA) CLKR0 (I/O/Z) ACLKR0 (I/O/Z) 22
23 (FPGA) (FPGA) (FPGA) / /HRD_HSTRB (I) (FPGA) CLKX0 (I/O/Z) ACLKX0 (I/O/Z) 23
24 (FPGA) (FPGA) (FPGA) / /HWR_HSTRB (I) (FPGA) FSR0 (I/O/Z) AFSR0 (I/O/Z) 24
25 (FPGA) Signal GND /HRDY (O) (FPGA) FSX0 (I/O/Z) AFSX0 (I/O/Z) 25
26 (FPGA) Signal GND /HINT (O) TXD (O) XF0 (I/O/Z) 26
27 (FPGA) Signal GND (FPGA) RTS (O) XF1 (I/O/Z) 27
28 (FPGA) Signal GND (FPGA) RXD (I) TOUT0 (O) AXR0[2] (I/O/Z) 28
29 (FPGA) Signal GND (FPGA) CTS (I) TOUT1 (O) AXR0[4] (I/O/Z) 29
30 (FPGA) Signal GND (FPGA) (FPGA) (FPGA) 30
31 (FPGA) Signal GND (FPGA) / SCL0 (FPGA) / /HOLD (I) (FPGA) 31
32 (FPGA) Signal GND (FPGA) / SDA0 (FPGA) / /HOLDA (O) Signal GND 32