Ultra DMA Timing, Mode MIN MAX | Maxtor 5120 specification

AT INTERFACE DESCRIPTION

Ultra DMA Timing

TIMING PARAMETERS (all times in nanoseconds)		MODE 0		MODE 1		MODE 2

		MIN	MAX	MIN	MAX	MIN	MAX

tCYC	Cycle Time (from STROBE edge to STROBE edge)	114		75		55
t2CYC	Two cycle time (from rising edge to next rising edge or	235		156		117
	from falling edge to next falling edge of STROBE)
tDS	Data setup time (at recipient)	15		10		7	70
tDH	Data hold time (at recipient)	5		5		5
tDVS	Data valid setup time at sender (time from data bus being	70		48		34	5
	valid until STROBE edge)
tDVH	Data valid hold time at sender (time from STROBE edge	6		6		6	20
	until data may go invalid)
tFS	First STROBE (time for device to send first STROBE)	0	230	0	200	0	170
tLI	Limited interlock time (time allowed between an action by	0	150	0	150	0	150
	one agent, either host or device, and the following action	0	150	0	150	0	150
	by the other agent)
tMLI	Interlock time with minimum	20		20		20
tUI	Unlimited interlock time	0		0		0
tAZ	Maximum time allowed for outputs to release		10		10		10
tZAH	Minimum delay time required for output drivers turning on	20		20		20
tZAD	(from released state)	0		0		0
tZAD		0		0		0
tENV	Envelope time (all control signal transitions are within the	20	70	20	70	20	70
	DMACK envelope by this much time)
tSR	STROBE to DMARDY (response time to ensure the		50		30		20
	synchronous pause case when the recipient is pausing)
tRFS	Ready-to-final-STROBE time (no more STROBE edges may		75		60		50
	be sent this long after receiving DMARDY- negation)
tRP	Ready-to-pause time (time until a recipient may assume	160		125		100
	that the sender has paused after negation of DMARDY-)
tIORDYZ	Pull-up time before allowing IORDY to be released		20		20		20
tZIORDY	Minimum time device shall wait before driving IORDY	0		0		0
tACK	Setup and hold times before assertion and negation of	20		20		20
	DMACK-
tSS	Time from STROBE edge to STOP assertion when the	50		50		50
	sender is stopping

DMARQ
(device)
tUI
DMACK-
(host)
tACK	tENV
STOP
(host)
tACK	tENV
HDMARDY-
(host)
tZIORDY
DSTROBE
(device)
tAZ
DD(15:0)
tACK
DA0, DA1, DA2,
CS0-, CS1-

tFS

tZAD
tFS
tZAD
tVDS	tDVH

Figure 5 - 4

Initiating an Ultra DMA Data In Burst

5 – 5

Image 37

Maxtor 5120 manual Ultra DMA Timing, Mode MIN MAX

Contents

HA RD Drive Produc T MA Nual 92048U8, 91792U7, 91536U6, 91280U5, 91024U4 and 90750U3 DiamondMax Plus Revisions Manual No U T I O N Before You Begin Contents Handling and Installation Product Specifications Host Software Interface AT Interface Description Service and Support Interface CommandsGlossary Figures Maxtor Corporation IntroductionManual Organization Abbreviations Conventions Signal ConventionsKey Words Numbering Product Description DiamondMax Plus 5120 Key Features Functional / Interface Product Features Logical Block Addressing On-the-Fly Hardware Error Correction Code ECCDefect Management Zone DMZ Software ECC Correction Cache Management Read-Ahead ModeBuffer Segmentation Automatic Write Reallocation AWR Major HDA Components Jumper Location/Configuration Subsystem ConfigurationCylinder Limitation Dual Drive Support Drive Configuration Product SpecificationsPerformance Specifications Models and Capacities Parameter Standard Metric Physical Dimensions Power Mode Definitions Power Requirements AverageEPA Energy Star Compliance Environmental Limits Shock and Vibration Reliability Specifications Radiated Electromagnetic Field Emissions EMC Compliance Safety Regulatory ComplianceCanadian Emissions Statement Hard Drive Handling Precautions Handling and InstallationPre-formatted Drive Important Notice Multi-pack Shipping Container Unpacking and Inspection Recommended Mounting Configuration Physical InstallationRepacking Tools for Installation Handling PrecautionsSystem Requirements Drive Identification Information Hard Drive Identification General Requirements Installing 5.25-inch Mounting Brackets and Rails Systems Using Cable SelectInstalling in a Device Bay Mounting Drive in System Attaching System Cables Attaching Interface and Power Cables Setting the Bios Cmos System SetupBios Cmos Parameters Hard Drive Preparation System Hangs During Boot AT Interface Description Interface ConnectorPin Description Summary Pin Description Table PIN Name Signal Name Signal Description PIO Timing Timing Parameters Mode DMA Timing Ultra DMA Timing Mode MIN MAX Sustained Ultra DMA Data In Burst Device Terminating an Ultra DMA Data In Burst Initiating an Ultra DMA Data Out Burst Device Pausing an Ultra DMA Data Out Burst Device Terminating an Ultra DMA Data Out Burst Features Register Error RegisterHost Software Interface Task File Registers Sector Number Register Sector Count RegisterCylinder Number Registers Device/Head Register Command Register Summary Command Name Command Code Parameters Used SDH Alternate Status Register Control Diagnostic RegistersDevice Control Register Digital Input Register Reset Handling Reset and Interrupt HandlingInterrupt Handling Set Feature Commands Interface Commands Read Sectors Read CommandsRead Verify Sectors Read Multiple Read DMA Set Multiple Mode Write CommandsWrite Sectors Write Verify Sectors Write DMA Write Multiple Set Features Mode Set Feature Commands Power Mode Commands Sleep Mode Identify Drive Initialization Commands 15-8 = PIO data transfer mode = Write Cache enabled Initialize Drive Parameters Execute Drive Diagnostic Seek, Format and Diagnostic CommandsFormat Track Execute S.M.A.R.T A.R.T. Command Set Service Policy Service and SupportNo Quibble Service Support Customer Service MaxFax ServiceInternet Glossary Access Time Cylinder Zero Gigabyte GB Logical Block Addressing Read Gate Signal THIN-FILM Media