Motorola PrPMC800/800ET Processor PMC Module manual Arbitration, Flash Memory, XCSR.XPAT1.DW

3 Functional Description

Table 3-2. Harrier Power-Up Configuration Settings (continued)

Harrier	Select	Default	Function/	Description
XAD	Option	Power-	Register Bit
Bus		Up
Signal		Setting
XAD[9]	BankB_SEL	x	Xport channel 0	Enable/Disable (1/0) Xport
			reset vector source	channel 0 (flash bank A) as
				reset vector source,
				depending on state of
				baseboard jumper.
XAD	Fixed	11	Xport channel 1 data	Set Xport channel 1 (flash
[8:7]			width	bank B) to 16-bit width, Hawk
			XCSR.XPAT1.DW	addressing mode.
XAD[6]	Fixed	1	Xport channel 1	Enable Xport channel 1 (flash
			reset vector source	bank B) as reset vector
				source if Xport channel 0 is
				disabled.
XAD	Fixed	xx	Xport channel 2 data	Unused.
[5:4]			width
			XCSR.XPAT2.DW
XAD[3]	Fixed	0	Xport channel 2	Disable Xport channel 2 as
			reset vector source	Reset Vector source
XAD	Fixed	xx	Xport channel 3 data	Unused.
[2:1]			width
			XCSR.XPAT2.DW
XAD[0]	Fixed	0	Xport Channel 3	Disable Xport channel 3 as
			Reset Vector Source	Reset Vector source

Arbitration

The Harrier ASIC contains arbiters for the PPC bus (60x bus mode only) and the PCI bus. The PPC arbiter is used to arbitrate between the processor and the Harrier PPC bus master for ownership of the PPC bus. The processor is connected to the Harrier arbiter CPU0_REQ/CPU0_GNT signal pair (XARB3/XARB0).

The Harrier PCI bus arbiter is disabled in the standard board configuration. Per the VITA-32 199x Processor PMC Standard, the PCI bus arbitration must be provided by the baseboard.

Flash Memory

The PrPMC800/800ET supports two banks of flash memory. Bank A is onboard flash, while bank B is optional flash located on the host board and accessed through the PMC P14 connector.

PrPMC800/800ET Processor PMC Module Installation and Use (PrPMC800A/IH5) 19