Motorola PrPMC800/800ET Processor PMC Module manual Functional Description, Features, Sdram

Functional Description

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Introduction

This chapter describes the PrPMC800/800ET Processor PMC Module on a block diagram level. The General Description provides an overview of the PrPMC800/800ET, followed by a detailed description of several blocks of circuitry. Figure 3-1 on page 15 shows a block diagram of the overall board architecture.

Detailed descriptions of other PrPMC800/800ET blocks, including programmable registers in the ASIC and peripheral chips, can be found in the PrPMC800/800ET Processor PMC Module Programmer’s Reference Guide and the Harrier ASIC Programmer’s Reference Guide, listed in Appendix C, Related Documentation. Refer to those documents for a more comprehensive set of functional descriptions.

Features

The following table summarizes the features of the PrPMC800/800ET processor module.

Table 3-1. PrPMC800/800ET Features

Feature	Description
Processor	Single MPC750-class or MPC7410 processor
	Core frequencies of 450 MHz for MPC750-class, 450Mhz and
	500Mhz for MPC7410, 400Mhz for MPC7410(N)
	Bus clock frequency of 100 MHz.
	Address and data bus parity
L2 Cache	Backside L2 Cache using pipeline burst-mode SRAMS:
	1MB for MPC750-class and MPC7410 (N), 2MB for the MPC7410
	Data bus parity
Flash Memory	Bank A: 32MB soldered on-board using two 128 Mbit devices.
	Bank B: Second bank of flash can be located on host board and
	accessed through the PMC P14 connector.
SDRAM	Double-Bit-Error detect, Single-Bit-Error correct across 72 bits
	Single bank of 16-bit wide devices onboard provide 64MB, 128MB,
	256MB, or 512MB SDRAM.
Memory Controller	Harrier’s SMC (System Memory Controller).
PCI Host Bridge	Harrier’s PHB (PCI Host Bridge).
Interrupt Controller	Harrier’s MPIC (Multi-Processor Interrupt Controller).

PrPMC800/800ET Processor PMC Module Installation and Use (PrPMC800A/IH5) 13