Chapter4 FunctionalOverview
7344/7334Hardware User Manual 4-6 ni.com
Host Communications
The host computer communicates with a 7344/7334 controller through a
numberof memory port addresses on the h ostbu s. The host bus can be any
oft he supported bus standards—PCI, PXI, or 1394.
The primary bidirectional data transfer port is at the base address of the
controller.This port supports FIFO data passing in both send and readback
directions. The 7344/7334 controller has both a command bufferfor
incoming commandsand a return data buffer(RDB) for readback data.
Ataddress offsets from the base address are two read-only status registers.
The communications status register (CSR) provides bits for
communications handshakingas well as real-time error reporting and
general status feedback to the host PC. The move complete status (MCS)
registerprovides instantaneous moti on status of all axes.