Tegra 200 Series Developer Board User Guide

3.1 Satellite Board Headers

All the interface connections between a satellite board and the Tegra 200 Series Developer Board are through two sets of

Samtec FTS series 50-pin Micro Strips connectors.

Table 2. Satellite Connectors Pinout

Dir

Pin #

Signal Name

 

Signal Name

Pin #

Dir

In

1

KB_COL7

 

EC_KSO17

2

Out

In

3

KB_COL6

 

EC_KSO16

4

Out

In

5

KB_COL5

 

EC_KSO15

6

Out

In

7

KB_COL4

 

EC_KSO14

8

Out

In

9

KB_COL3

 

EC_KSO13

10

Out

In

11

KB_COL2

 

EC_KSO12

12

Out

In

13

KB_COL1

 

EC_KSO11

14

Out

In

15

KB_COL0

 

EC_KSO10

16

Out

Out

17

KB_ROW15

 

EC_KSO9

18

Out

Out

19

KB_ROW14

 

EC_KSO8

20

Out

Out

21

KB_ROW13

 

EC_KSO7

22

Out

Out

23

KB_ROW12

 

EC_KSO6

24

Out

Out

25

KB_ROW11

 

EC_KSO5

26

Out

Out

27

KB_ROW10

 

EC_KSO4

28

Out

Out

29

KB_ROW9

 

EC_KSO3

30

Out

Out

31

KB_ROW8

 

EC_KSO2

32

Out

Out

33

KB_ROW7

 

EC_KSO1

34

Out

Out

35

KB_ROW6

 

EC_KSO0

36

Out

Out

37

KB_ROW5

 

EC_KSI7

38

In

Out

39

KB_ROW4

 

EC_KSI6

40

In

Out

41

KB_ROW3

 

EC_KSI5

42

In

Out

43

KB_ROW2

 

EC_KSI4

44

In

Out

45

KB_ROW1

 

EC_KSI3

46

In

Out

47

KB_ROW0

 

EC_KSI2

48

In

In

49

EC_KSI0

 

EC_KSI1

50

In

 

 

 

 

 

 

 

Dir

Pin #

Signal Name

 

Signal Name

Pin #

Dir

 

Out

1

LED_WPAN*

 

VDD_CELL_RMT

2

In

Out

3

LED_WLAN*

 

UART4_TXD

4

Out

 

Out

5

LED_WWAN*

 

VDDIO_NAND_MB

6

Out

 

In

7

W_DISABLE *

 

UART4_RXD

8

In

 

Out

9

LED_WIFI_BT *

 

UART4_CTS*

10

In

 

Out

11

LED_CHARGE*

 

UART4_RTS*

12

Out

 

Out

13

LED_POWER*

 

NO CONNECT

14

 

 

 

Out

15

LED_SCROLL_LOCK*

 

FORCE_ACOK

16

In

 

Out

17

LED_CAPS_LOCK*

 

VDDIO_SYS_MB

18

Out

 

Out

19

LED_NUM_LOCK*

 

PWR_I2C_SCL

20

Bi

 

 

21

GND

 

PWR_I2C_SDA

22

Bi

 

 

In

23

SPDIF_IN

 

VDD_3V3_MB

24

Out

 

Out

25

SPDIF_OUT

 

VDD_3V3_MB

26

Out

 

 

27

GND

 

GND

28

 

 

 

 

Out

29

IR_TXD

 

PS2_TS_CLOCK

30

Bi

 

In

31

IR_RXD

 

PS2_TS_DATA

32

Bi

 

In

33

LID_OPEN*

 

GND

34

 

 

 

Out

35

VDD_5V0_MB

 

CAM_I2C_SDA

36

Bi

 

Out

37

VDD_5V0_MB

 

CAM_I2C_SCL

38

Bi

 

In

39

TP_IRQ*

 

GND

40

 

 

 

In

41

TS_IRQ*

 

PS2_TP_CLOCK

42

Bi

 

 

43

NO CONNECT

 

PS2_TP_DATA

44

Bi

 

 

In

45

ONKEY*

 

LED_HEARTBEAT*

46

Out

 

In

47

FORCE_RECOVERY*

 

SYS_RESET_B*

48

Out

 

In

49

RESET*

 

VDD_3V3_EC_MB

50

Out

 

 

 

 

 

 

 

 

DG-04927-001_v01

Advance Information – Subject to Change

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