Figure 24. Debug Interface Connection
Tegra
Tegra 200 Series Developer Board User Guide
VDDIO_SYS | VDDIO_SYS |
| ONKEY_N |
| 10KΩ |
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10KΩ |
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AUDIO
1.8V VDDIO_AUDIO
UART
1.8V VDDIO_UART
SYSTEM
1.8V VDDIO_SYS
LCD
1.8V VDDIO_LCD
SPI1_SCK SPI1_CS0_N SPI1_MOSI SPI1_MISO
UART1_TXD UART1_RXD
JTAG_RTCK
JTAG_TCK
JTAG_TDI
JTAG_TDO JTAG_TMS JTAG_TRST_N
LCD_PWR1
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| 100KΩ |
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| DBG_IRQ_N |
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Unused Pins
If JTAG is not implemented, then JTAG_RTCK and JTAG_TDO can be left unconnected. The JTAG_TDI and JTAG_TMS pins still need to be pulled up, and JTAG_TRST_N and JTAG_TCK must be pulled down. The rail the JTAG pins reside on (VDDIO_SYS) must be powered for any mode including Deep Sleep.
4.9.3 EFUSE
The Tegra 250 design must provide a way to supply a 3.3V power source to the FUSE_SRC pin. This can be accomplished using one of the following mechanisms:
Test point to connect external 3.3V supply
3.3V Output of
3.3V Output of PMU, controlled by PWR_I2C from the Tegra 250
Permanently connected to
The power source must provide a nominal voltage of 3.3V and be able to supply a minimum of 100mA. When not powered, a 10K Ω
Figure 25. EFUSE Connections
Advance Information – Subject to Change | 36 | |
| NVIDIA CONFIDENTIAL |
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