NXP Semiconductors TDA8932B 8.3 Pulse width modulation frequency

TDA8932B_3 © NXP B.V. 21 June 2007. All rights reserved.

Product data sheet Rev. 03— 21 June 2007 7 of 48

NXP Semiconductors TDA8932B

Class-D audio ampliﬁer

8.3 Pulse width modulation frequency

The output signal of the ampliﬁer is a PWM signal with a carrier frequency of

approximately 320 kHz. Using a 2nd-order low-pass ﬁlter in the application results in an

analog audio signal across the loudspeaker. The PWM switching frequency can be set by

an external resistor Rosc connected between pins OSCREF and VSSD(HW). The carrier

frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39 kΩ,

the carrier frequency is set to an optimized value of 320 kHz (see Figure 5).

If two or more TDA8932B devices are used in the same audio application, it is

recommended to synchronize the switching frequency of all devices. This can be realized

by connecting all pins OSCIO together and conﬁgure one of the TDA8932B in the

application as clock master, while the other TDA8932B devices are conﬁgured in slave

mode.

Pin OSCIO is a 3-state input or output buffer. Pin OSCIO is conﬁgured in master mode as

oscillator output and in slave mode as oscillator input. Master mode is enabled by applying

a resistor while slave mode is entered by connecting pin OSCREF directly to pin VSSD(HW)

(without any resistor).

The value of the resistor also sets the frequency of the carrier which can be estimated by

the following formula:

Fig 4. Start-up sequence

VP

POWERUP

DREF

HVPREF

HVP1, HVP2

ENGAGE

2.0 V (typical)

1.2 V (typical)

audio

PWM

OUT1, OUT2

DIAG

OSCIO

001aaf885

operating operating

PWMPWM

sleepmute operating fault

AUDIO AUDIO AUDIO

≤ 0.8 V

Contents

Main 1. General description 2. Features 3. Applications TDA8932B Rev. 03 21 June 2007 Product data sheet Class-D audio amplier NXP Semiconductors TDA8932B 4. Quick reference data =25 5. Ordering information = 22 V; f = 320 kHz; T 6. Block diagram Fig 1. Block diagram Product data sheet Rev. 03 21 June 2007 4 of 48 7. Pinning information TDA8932BTW TDA8932BT 7.1 Pinning Fig 2. Pin conguration SO32 Fig 3. Pin conguration HTSSOP32 8. Functional description 8.1 General 8.2 Mode selection and interfacing 8.3 Pulse width modulation frequency NXP Semiconductors TDA8932B 8.4 Protection NXP Semiconductors TDA8932B 8.4.1 Thermal Foldback (TF) 8.4.2 OverTemperature Protection (OTP) 8.4.3 OverCurrent Protection (OCP) 8.4.4 Window Protection (WP) 8.5 Diagnostic input and output 8.6 Differential inputs 8.7 Output voltage buffers 4 DIAG HVPREF. 9. Internal circuitry Table 7. Internal circuitry 1V 16 V 17 V 32 V 2 IN1P 3 IN1N 12 INREF 14 IN2N 15 IN2P 5 ENGAGE 6 POWERUP 7 CGND 8V Table 7. Internal circuitry (Continued) 9V 10 OSCREF 18 DREF 11 HVPREF 13 TEST Page 10. Limiting values 11. Thermal characteristics In accordance with the Absolute Maximum Rating System (IEC 60134). 12. Static characteristics Page 13. Dynamic characteristics =25 4 =2 = 22 V; T =2 4 =8 = 320 kHz; R =8 = 320 kHz; R 14. Application information 14.1 Output power estimation a. THD+N = 0.5 % b. THD+N = 10 % Fig 8. SE output power as a function of supply voltage a. THD+N = 0.5 % b. THD+N = 10 % Fig 9. BTL output power as a function of supply voltage 14.2 Output current limiting 14.3 Speaker conguration and impedance 14.4 Single-ended capacitor 14.5 Gain reduction 14.6 Device synchronization 14.7 Thermal behavior (printed-circuit board considerations) 14.8 Pumping effects Fig 12. SE application for reducing pumping effects 14.9 SE curves measured in reference design a. VP=22V; R Fig 14. Total harmonic distortion-plus-noise as a function of frequency Fig 13. Total harmonic distortion-plus-noise as a function of output power per channel (1) fi= 6 kHz (2) fi= 100 Hz (3) fi= 1 kHz Vi= 100 mV (RMS); Ri=0; Cse = 1000 F (1) VP= 30 V; RL=28 (2) VP= 22 V; RL=24 Vripple = 500 mV (RMS) referenced to ground; Ri=0 (shorted input) (1) VP=30V; R (2) VP=22V; R Ri=0; 20 kHz brick-wall lter AES17 (1) VP= 22 V; RL=24 (2) VP= 30 V; RL=28 Po= 1 W; CHVPREF =47F voltage = ------------------------- per channel (two channels driven) fi= 1 kHz; (1) VP= 22 V; RL=24 (2) VP= 30 V; RL=28 NXP Semiconductors TDA8932B ENGAGE Fig 23. Output power per channel as a function of time board (55 mm 45 mm) without heat sink (1) VP=22V (2) VP=26V (3) VP=29V 14.10 BTL curves measured in reference design a. VP=12V; R Fig 27. Total harmonic distortion-plus-noise as a function of frequency Fig 26. Total harmonic distortion-plus-noise as a function of output power (1) fi= 6 kHz (2) fi= 1 kHz (3) fi= 100 Hz Vi= 100 mV (RMS); Ri=0 (1) VP= 12 V; RL=4 (2) VP= 22 V; RL=8 Vripple = 500 mV (RMS) referenced to ground; Ri=0 (shorted input) (2) VP=12V; R Ri=0; 20 kHz brick-wall lter AES17 (1) RL=4; VP=12V (2) RL=8; VP=22V fi= 1 kHz (short time PO); dashed line will require board (55 mm 45 mm) without heat sink = -------------------- Fig 32. Output power as a function of time (1) VP=12V (2) VP= 13.5 V (3) VP=15V Fig 35. Power dissipation as a function of supply voltage 14.11 Typical application schematics (simplied) Fig 36. Typical simplied application diagram for 2 SE (asymmetrical supply) Fig 37. Typical simplied application diagram for 1 BTL (asymmetrical supply) Fig 38. Typical simplied application diagram for 2 SE (symmetrical supply) 15. Test information Fig 39. Typical simplied application diagram for 1 BTL (symmetrical supply) 15.1 Quality information is applicable. General Quality Specication for Integrated Circuits, SNW-FQ-611 16. Package outline Fig 40. Package outline SOT287-1 (SO32) SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 Fig 41. Package outline SOT549-1 (HTSSOP32) 32 17 116 17. Soldering 17.4 Reow soldering For further information on temperature proles, refer to Application Note 18. Abbreviations AN10365 Surface mount reow soldering description . 19. Revision history Product data sheet Rev. 03 21 June 2007 47 of 48 20. Legal information 20.1 Data sheet status 20.2 Denitions 20.3 Disclaimers 20.4 Trademarks 22. Contents