4.1.2Start of Conversion Register
The start of conversion register is
1.When configured for internal triggering, writing a "0" to this register generates the software trigger, starting the data conversion process.
2.Writing a "0" to this register at any time resets the VALID bit in the control word register. This allows the VALID bit to be reset at any time during the conversion
process or before the event of an external trigger.
4.1.3DAC0 Register
An output to this register causes the lower twelve bits of data to be converted to an analog output on D/A converter channel 0. The four most significant bits of data are ignored. This register is
4.1.4DAC1 Register
An output to this register causes the lower twelve bits of data to be converted to an analog output on D/A converter channel 1. The four most significant bits of data are ignored. This register is
The remaining four registers are contained in an 8254 counter/timer.
4.1.5Clock Rate Register (low word)
The low word of the clock divider is contained in counter 0 of an 8254 counter/timer. The output of this counter is cascaded into the input of counter 1 to produce a
4.1.6Clock Rate Register (high word)
The high word of the clock divider is contained in counter 1 of the 8254 counter/timer. Mode 2 must be selected for counter 1 with a minimum count of 2. This register is
4.1.7Multi-Function Timer Register
The
4.1.88254 Control Word/Status Register
This register is used to program the mode and report the status of the 8254 counter/timer. This register is
27 |
