Omron C200HE, C200HG, C200HX - page 393

382

Output ON delay: 15 ms

Cycle time for PC of Unit 0: 20 ms

Cycle time for PC of Unit 7: 50 ms

Minimum transmission time: 2.8 ms+10 ms=12.8 ms

The following diagram illustrates the data flow that will produce the maximum

response time. Delays occur because signals or data is received just after they

would be processed or because data is sent during processing. In either case,

processing must wait until the next scan/polling cycle.

First output to the buffer in the polling unit is delayed by the setting of the number

of LR bits to be refreshed each scan. A similar delay is present when the LR data

reaches Unit 7. The polling delay is the result of the LR data in its PC being up-

dated immediately after the previous was sent to the buffer in the PC Link Unit,

cause a delay until the next polling cycle. One more polling cycle is then required

before the data reaches the buffer in PC Link Unit 7.

PC with

Unit 0

Buffer in Unit 0

PC Link Unit

transmissions

Buffer in Unit 7

PC with

Unit 7

Input

Output

PC Link

polling time

Cycle time

Cycle time I/O refresh

Induction sequence

processing time

Maximum

transmission

time

Polling delay

The equation for maximum I/O response time is thus as follows:

Response time = Input ON delay + [Cycle time of PC of Unit 0 × (Number of LR

transfer bits ÷ I/O refresh bits)] + α + (PC Link polling time +

Induction sequence processing time) + {Cycle time of PC of

Unit 7 × [(Number of LR transfer bits ÷ I/O refresh bits) × 2 + 1]}

+ β + Output ON delay

If cycle time of PC of Unit 0 > PC Link polling time, α = cycle time of PC of Unit 0. If

cycle time of PC of Unit 0 < PC Link polling time, α = PC Link polling time.

If cycle time of PC of Unit 7 > PC Link polling time, β = cycle time of PC of Unit 7. If

cycle time of PC of Unit 7 < PC Link polling time, β = PC Link polling time.

Inserting the following values into this equation produces a maximum I/O re-

sponse time of 661.3 ms.

Input ON delay: 1.5 ms

Output ON delay: 15 ms

Cycle time for PC of Unit 0: 20 ms

Cycle time for PC of Unit 7: 50 ms

PC Link polling time: 2.8 ms × 8 PCs + 10 ms = 32.4 ms

Induction sequence processing: 15 ms × (8 PCs – 8 PCs) = 0 ms

Maximum Response Time

I/O Response Time Section 6-4

Contents

Main Page v Notice: DANGER WARNING OMRON Product References Visual Aids PRECAUTIONS xiii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SECTION 1 Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SECTION 2 Hardware Considerations 11. . . . . . . . . . . . . . . . . . . . . . . . . SECTION 3 Memory Areas 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SECTION 4 Writing and Inputting the Program 73. . . . . . . . . . . . . . . . . SECTION 5 Instruction Set 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SECTION 6 Program Execution Timing 359. . . . . . . . . . . . . . . . . . . . . . . . SECTION 7 Program Monitoring and Execution 389. . . . . . . . . . . . . . . . Page xi About this Manual: WARNING xiii PRECAUTIONS xiv Safety Precautions 3 1 Intended Audience 2 General Precautions WARNING 3 Safety Precautions WARNING 4 Operating Environment Precautions 5 Application Precautions WARNING xvi Application Precautions 5 Page SECTION 1 Introduction 2 The Origins of PC Logic Section 1-2 1-1 Overview 1-2 The Origins of PC Logic 3 PC Terminology Section 1-3 1-3 PC Terminology 4 Overview of PC Operation Section 1-5 1-4 OMRON Product Terminology 1-5 Overview of PC Operation 5 Peripheral Devices Section 1-6 1-6 Peripheral Devices 6 Available Manuals Section 1-7 1-7 Available Manuals 1-8 C200HX/HG/HE Features 1-8-1 C200HS and C200HX/HG/HE Capabilities 8 C200HX/HG/HE Features Section 1-8 1-8-2 Program Compatibility Page Page SECTION 2 Hardware Considerations 12 CPU Unit Components Section 2-1 2-1 CPU Unit Components 13 CPU Unit Components Section 2-1 2-1-1 CPU Unit Indicators 2-1-2 Peripheral Device Connection Page 15 CPU Unit Capabilities Section 2-3 2-2 PC Configuration 2-3 CPU Unit Capabilities 2-4 Memory Cassettes 2-4-1 Hardware and Software Settings 2-4-2 Writing/Reading UM Data 2-4-3 Writing/Reading IOM Data Page 20 CPU Unit DIP Switch Section 2-5 2-5 CPU Unit DIP Switch The 6 pins on the DIP switch control 6 of the CPU Units operating parameters. 21 Operating without a Backup Battery Section 2-6 2-6 Operating without a Backup Battery 22 Operating without a Backup Battery Section 2-6 SECTION 3 Memory Areas 24 Introduction Section 3-1 3-1 Introduction 3-1-1 Data Area Overview 3-1-2 IR/SR Area Overview 3-2 Data Area Structure Page 27 Signed and Unsigned Binary Data Converting Decimal to Signed Binary 3-3 IR (Internal Relay) Area Page Page Page 3-4 SR (Special Relay) Area Page Page Page Page 3-4-1 SYSMAC NET/SYSMAC LINK System Loop Status SR 236 provides the local node loop status for SYSMAC NET Systems, as shown below. SYSMAC NET 3-4-2 Remote I/O Systems 40 3-4-3 Link System Flags and Control Bits Host Link Systems PC Link Systems Multilevel PC Link Systems 3-4-4 Forced Status Hold Bit 3-4-5 I/O Status Hold Bit 3-4-6 Output OFF Bit 3-4-7 FAL (Failure Alarm) Area 3-4-8 Low Battery Flag 3-4-9 Cycle Time Error Flag 3-4-10 I/O Verification Error Flag 3-4-11 First Cycle Flag 3-4-12 Clock Pulse Bits 3-4-13 Step Flag 3-4-14 Group-2 Error Flag 3-4-15 Special Unit Error Flag 3-4-16 Instruction Execution Error Flag, ER 3-4-17 Arithmetic Flags 3-4-18 Interrupt Subroutine Areas 3-4-19 RS-232C Port Communications Areas 3-4-20 Peripheral Port Communications Areas 3-4-21 Memory Cassette Areas 3-4-22 Data Transfer Error Bits 3-4-23 Ladder Diagram Memory Areas 3-4-24 Memory Error Flags 3-4-25 Data Save Flags 3-4-26 Transfer Error Flags 3-5 AR (Auxiliary Relay) Area Page 3-5-1 Restarting Special I/O Units 3-5-2 Slave Rack Error Flags 3-5-3 Group-2 Error Flags 3-5-4 Optical I/O Unit and I/O Terminal Error Flags 3-5-5 SYSMAC LINK System Data Link Settings 3-5-6 Error History Bits 3-5-7 Active Node Flags 3-5-8 SYSMAC LINK/SYSMAC NET Link System Service Time 3-5-9 Calendar/Clock Area and Bits 3-5-10 TERMINAL Mode Key Bits 3-5-11 Power OFF Counter 3-5-12 SYSMAC LINK Peripheral Device Flags 3-5-13 Cycle Time Flag 3-5-14 Link Unit Mounted Flags 3-5-15 CPU Unit-mounting Device Mounted Flag 3-5-16 FPD Trigger Bit 3-5-17 Data Tracing Flags and Control Bits 3-6 DM (Data Memory) Area 3-6-1 Expansion DM Area 3-6-2 Special I/O Unit Data 3-6-3 Error History Area Page 3-6-4 PC Setup Page Page Page Page 3-6-5 Communications Board Settings Page 3-6-6 Special I/O Unit Area Settings 68 TC (Timer/Counter) Area Section 3-8 3-7 HR (Holding Relay) Area 3-8 TC (Timer/Counter) Area 69 LR Area Section 3-9 3-9 LR (Link Relay) Area 70 UM Area Section 3-10 3-10 UM Area 71 EM (Extended Data Memory) Area Section 3-12 3-11 TR (Temporary Relay) Area 3-12 EM (Extended Data Memory) Area 3-12-1 Using the EM Area 72 EM (Extended Data Memory) Area Section 3-12 3-12-2 The Current EM Bank SECTION 4 Writing and Inputting the Program 74 Instruction Terminology Section 4-2 4-1 Basic Procedure 4-2 Instruction Terminology 4-3 Program Capacity 4-4 Basic Ladder Diagrams 4-4-1 Basic Terms 4-4-2 Mnemonic Code 4-4-3 Ladder Instructions Page Page 4-4-4 OUTPUT and OUTPUT NOT 4-4-5 The END Instruction 4-4-6 Logic Block Instructions Page Page Page Page Page Page 88 The Programming Console Section 4-5 4-4-7 Coding Multiple Right-hand Instructions 4-5 The Programming Console 4-5-1 The Keyboard Page 90 The Programming Console Section 4-5 4-5-2 PC Modes 4-5-3 The Display Message Switch 4-6 Preparation for Operation 4-6-1 Entering the Password 4-6-2 Buzzer 4-6-3 Clearing Memory Page Page 4-6-4 Registering the I/O Table 4-6-5 Clearing Error Messages 4-6-6 Verifying the I/O Table Page 4-6-7 Reading the I/O Table 100 Meaning of Displays 4-6-8 Clearing the I/O Table 4-6-9 SYSMAC NET Link Table Transfer Page 4-7 Inputting, Modifying, and Checking the Program 4-7-1 Setting and Reading from Program Memory Address 4-7-2 Entering and Editing Programs Page Page 4-7-3 Checking the Program Page 4-7-4 Displaying the Cycle Time 4-7-5 Program Searches 4-7-6 Inserting and Deleting Instructions Page Page 4-7-7 Branching Instruction Lines Page Page Page 4-7-8 Jumps 120 Controlling Bit Status Section 4-8 4-8 Controlling Bit Status 121 Controlling Bit Status Section 4-8 4-8-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN 4-8-2 KEEP 4-8-3 Self-maintaining Bits (Seal) 122 Work Bits (Internal Relays) Section 4-9 4-9 Work Bits (Internal Relays) 123 Work Bits (Internal Relays) Section 4-9 124 Programming Precautions Section 4-10 4-10 Programming Precautions 125 Programming Precautions Section 4-10 4-11 Program Execution 4-12 Special I/O Unit Interface Programs 4-12-1 Restarting Special I/O Units 4-12-2 Special I/O Unit Error Processing Program 4-12-3 Changing the Special I/O Unit Settings 4-12-4 Special I/O Unit I/O Refreshing Interval 4-12-5 Reducing the Cycle Time 4-13 Analog Timer Unit Programming 4-13-1 Operation 4-13-2 Bit Allocation and DIP Switch Settings 4-13-3 Example Program Unit Settings and Wiring Ladder Program SECTION 5 Instruction Set Page Page 138 Data Areas, Definer Values, and Flags Section 5-3 5-1 Notation 5-2 Instruction Format 5-3 Data Areas, Definer Values, and Flags 139 Data Areas, Definer Values, and Flags Section 5-3 140 Differentiated Instructions Section 5-4 5-4 Differentiated Instructions 141 Expansion Instructions Section 5-5 5-5 Expansion Instructions 5-6 Coding Right-hand Instructions The following diagram and corresponding mnemonic code illustrates the points described above. Page 5-7 Instruction Set Lists 5-7-1 Function Codes Left Right digit digit 0 1 2 3 4 5 6 7 8 9 0 1 2 Page Page Page 149 Ladder Diagram Instructions Section 5-8 5-8 Ladder Diagram Instructions 5-8-1 LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT 5-8-2 AND LOAD and OR LOAD 5-9 Bit Control Instructions 5-9-1 OUTPUT and OUTPUT NOT OUT and OUT NOT 5-9-2 DIFFERENTIATE UP and DOWN DIFU(13) and DIFD(14) Page 5-9-3 SET and RESET SET and RSET 5-9-4 KEEP KEEP(11) 155 INTERLOCK and INTERLOCK CLEAR IL(02) and ILC(03) Section 5-10 NEVER 5-10 INTERLOCK and INTERLOCK CLEAR IL(02) and ILC(03) 156 INTERLOCK and INTERLOCK CLEAR IL(02) and ILC(03) Section 5-10 157 JUMP and JUMP END JMP(04) and JME(05) Section 5-11 5-11 JUMP and JUMP END JMP(04) and JME(05) 5-12 END END(01) 5-13 NO OPERATION NOP(00) 5-14 Timer and Counter Instructions 5-14-1 TIMER TIM Page Page Example 4: One-Shot Bits Page 5-14-2 HIGH-SPEED TIMER TIMH(15) 5-14-3 TOTALIZING TIMER TTIM(87) 5-14-4 COUNTER CNT Page Page 5-14-5 REVERSIBLE COUNTER CNTR(12) Page 5-15 Data Shifting 5-15-1 SHIFT REGISTER SFT(10) Page 5-15-2 REVERSIBLE SHIFT REGISTER SFTR(84) Limitations St and E must be in the same data area and St must be less than or equal to E. Page 5-15-3 ARITHMETIC SHIFT LEFT ASL(25) 5-15-4 ARITHMETIC SHIFT RIGHT ASR(26) 5-15-5 ROTATE LEFT ROL(27) 5-15-6 ROTATE RIGHT ROR(28) 5-15-7 ONE DIGIT SHIFT LEFT SLD(74) ... 5-15-8 ONE DIGIT SHIFT RIGHT SRD(75) 5-15-9 WORD SHIFT WSFT(16) 5-15-10 ASYNCHRONOUS SHIFT REGISTER ASFT(17) Page 5-16 Data Movement 5-16-1 MOVE MOV(21) 5-16-2 MOVE NOT MVN(22) 5-16-3 BLOCK SET BSET(71) 5-16-4 BLOCK TRANSFER XFER(70) N: Number of words (BCD) S: Starting source word D: Starting destination word XFER(70) 5-16-5 DATA EXCHANGE XCHG(73) 5-16-6 SINGLE WORD DISTRIBUTE DIST(80) Page 5-16-7 DATA COLLECT COLL(81) Page EQ: ON when the transferred data is zero; otherwise OFF. 5-16-8 MOVE BIT MOVB(82) S: Source word IR, SR, AR, DM, HR, LR, # Bi: Bit designator (BCD) D: Destination word MOVB(82) Bi 5-16-9 MOVE DIGIT MOVD(83) Digit Designator The following show examples of the data movements for various values of Di. Note Up to 255 (FF) bits can be copied at one time. 5-16-10 TRANSFER BITS XFRB(62) C: Control word IR, SR, AR, DM, TC, HR, LR, # S: First source word XFRB(62) @XFRB(62) 5-16-11 EM BLOCK TRANSFER XFR2() 5-16-12 EM BANK TRANSFER BXF2() 5-17 Data Comparison 5-17-1 MULTI-WORD COMPARE MCMP(19) 5-17-2 COMPARE CMP(20) Page Page 5-17-3 DOUBLE COMPARE CMPL(60) 5-17-4 BLOCK COMPARE BCMP(68) Page 5-17-5 TABLE COMPARE TCMP(85) 5-17-6 AREA RANGE COMPARE ZCP(88) 5-17-7 DOUBLE AREA RANGE COMPARE ZCPL() 5-17-8 SIGNED BINARY COMPARE CPS() 5-17-9 DOUBLE SIGNED BINARY COMPARE CPSL() 5-18 Data Conversion 5-18-1 BCD-TO-BINARY BIN(23) 5-18-2 DOUBLE BCD-TO-DOUBLE BINARY BINL(58) 5-18-3 BINARY-TO-BCD BCD(24) 5-18-4 DOUBLE BINARY-TO-DOUBLE BCD BCDL(59) 5-18-5 HOURS-TO-SECONDS SEC(65) 5-18-6 SECONDS-TO-HOURS HMS(66) 5-18-7 4-TO-16/8-TO-256 DECODER MLPX(76) Page Page 5-18-8 16-TO-4/256-TO-8 ENCODER DMPX(77) Example: 4-bit to 16-bit Decoding Page Page 5-18-9 7-SEGMENT DECODER SDEC(78) S: Source word (binary) Di: Digit designator SDEC(78) Di Page Flags ER: Incorrect digit designator, or data area for destination exceeded 5-18-10 ASCII CONVERT ASC(86) 5-18-11 ASCII-TO-HEXADECIMAL HEX() Page Page 5-18-12 SCALING SCL() Page 5-18-13 COLUMN TO LINE LINE(63) 5-18-14 LINE TO COLUMN COLM(64) 5-18-15 2S COMPLEMENT NEG() 5-18-16 DOUBLE 2S COMPLEMENT NEGL() 5-19 BCD Calculations 5-19-1 INCREMENT INC(38) 5-19-2 DECREMENT DEC(39) 229 5-19-3 SET CARRY STC(40) 5-19-4 CLEAR CARRY CLC(41) 5-19-5 BCD ADD ADD(30) Au + Ad + CY CY R 5-19-6 DOUBLE BCD ADD ADDL(54) + 231 5-19-7 BCD SUBTRACT SUB(31) Mi Su CY CY R Page 5-19-8 DOUBLE BCD SUBTRACT SUBL(55) Flags ER: Mi, M+1,Su, and Su+1 are not BCD. First subtraction Second subtraction Turned ON to indicate negative result. 5-19-9 BCD MULTIPLY MUL(32) 5-19-10 DOUBLE BCD MULTIPLY MULL(56) x 5-19-11 BCD DIVIDE DIV(33) 5-19-12 DOUBLE BCD DIVIDE DIVL(57) 5-19-13 FLOATING POINT DIVIDE FDIV(79) Page 0.4369620 x 10 5-19-14 SQUARE ROOT ROOT(72) In this example, 6017 = 77.56, and 77.56 is rounded off to 78. 5600 > 4900 243 5-20 Binary Calculations 5-20-1 BINARY ADD ADB(50) Au + Ad + CY CY R Page 245 5-20-2 BINARY SUBTRACT SBB(51) Mi Su CY CY R Page Page 5-20-3 BINARY MULTIPLY MLB(52) 5-20-4 BINARY DIVIDE DVB(53) 5-20-5 DOUBLE BINARY ADD ADBL() + Page 5-20-6 DOUBLE BINARY SUBTRACT SBBL() Page 5-20-7 SIGNED BINARY MULTIPLY MBS() 5-20-8 DOUBLE SIGNED BINARY MULTIPLY MBSL() x 5-20-9 SIGNED BINARY DIVIDE DBS() 5-20-10DOUBLE SIGNED BINARY DIVIDE DBSL() 5-21 Special Math Instructions 5-21-1 FIND MAXIMUM MAX() 5-21-2 FIND MINIMUM MIN() 5-21-3 AVERAGE VALUE AVG() Page 5-21-4 SUM SUM() C: Control data IR, SR, AR, DM, HR, LR, # R1: First word in range SUM() R @SUM() Page 5-21-5 ARITHMETIC PROCESS APR(69) 264 Examples C: Input data, x Result data Input data, x Result data C+(2m+1) X C+(2m+2) Y 5-21-6 PID CONTROL PID() Page Parameter Settings Page Page Page Page Page Program 5-22 Logic Instructions Example 5-22-1 COMPLEMENT COM(29) Wd: Complement word COM(29) Wd 5-22-2 LOGICAL AND ANDW(34) 5-22-3 LOGICAL OR ORW(35) 5-22-4 EXCLUSIVE OR XORW(36) 5-22-5 EXCLUSIVE NOR XNRW(37) 5-23 Subroutines and Interrupt Control 5-23-1 Subroutines 5-23-2 Interrupts Page Page 5-23-3 SUBROUTINE ENTER SBS(91) 5-23-4 SUBROUTINE DEFINE and RETURN SBN(92)/RET(93) 5-23-5 MACRO MCRO(99) Page 5-23-6 INTERRUPT CONTROL INT(89) Page Page Page 5-24 Step Instructions 5-24-1 STEP DEFINE and STEP STARTSTEP(08)/SNXT(09) Page 293 Examples Page Page Page Page Page Page 5-25 Special Instructions 5-25-1 FAILURE ALARM FAL(06) and SEVERE FAILURE ALARM FALS(07) 5-25-2 CYCLE TIME SCAN(18) 5-25-3 TRACE MEMORY SAMPLING TRSM(45) 5-25-4 MESSAGE DISPLAY MSG(46) 5-25-5 LONG MESSAGE LMSG(47) 5-25-6 TERMINAL MODE TERM(48) 5-25-7 WATCHDOG TIMER REFRESH WDT(94) 5-25-8 I/O REFRESH IORF(97) 5-25-9 GROUP-2 HIGH-DENSITY I/O REFRESH MPRF(61) 5-25-10 BIT COUNTER BCNT(67) 5-25-11 FRAME CHECKSUM FCS() Page 5-25-12 FAILURE POINT DETECTION FPD() Page Page Flags ER: T is not BCD. C is not a constant or the rightmost two digits of C are not BCD 00 to 99. 5-25-13 DATA SEARCH SRCH() 5-25-14 EXPANSION DM READ XDMR() 5-25-15 INDIRECT EM ADDRESSING IEMS() 5-25-16 SELECT EM BANK EMBC() 318 5-26 Network Instructions 5-26-1 NETWORK SEND SEND(90) Control Data Page Controller Link Systems @SEND(90) 321 Indirect Destination Beginning Word Designations Page 5-26-2 NETWORK RECEIVE RECV(98) 324 Control Data Ethernet Systems Refer to the PC Card Unit Operation Manual for details. SYSMAC LINK Systems Refer to the SYSMAC LINK System Manual for details. Controller Link Systems @RECV(98) L 326 Indirect Destination Beginning Word Designations 5-26-3 About Network Communications Page 5-27 Serial Communications Instructions 5-27-1 RECEIVE RXD() C: Control word N: Number of bytes RXD() Page 5-27-2 TRANSMIT TXD() Page 5-27-3 CHANGE RS-232C SETUP STUP() S Function Word address The contents of S through S+4 are copied to the part of the PC Setup ues. The following table shows the function of the transferred setup data. 5-27-4 PROTOCOL MACRO PMCR() 5-28 Advanced I/O Instructions 5-28-1 7-SEGMENT DISPLAY OUTPUT 7SEG() Page Page 5-28-2 DIGITAL SWITCH INPUT DSW() Page The following example illustrates connections for an A7B Thumbwheel Switch. ID212 Input Unit Output Unit OD212 Switch no. 8 Page 5-28-3 HEXADECIMAL KEY INPUT HKY() ID212 Input Unit OD212 Output Unit Page 5-28-4 TEN KEY INPUT TKY() Flags ER: Indirectly addressed DM word is non-existent. (Content of DM word is 5-28-5 MATRIX INPUT MTR() Page 5-29 Special I/O Unit Instructions 5-29-1 SPECIAL I/O UNIT READ IORD() 5-29-2 SPECIAL I/O UNIT WRITE IOWR() Page 5-29-3 PCMCIA CARD MACRO CMCR() Process Number The process number (1 through 4) determines what function CMCR() will per- form. Page Page Page SECTION 6 Program Execution Timing 6-1 Cycle Time Flowchart of CPU Unit Operation Note A minimum cycle time can be set either in DM 6619 of the PC Setup or by executing SCAN(18). Page PC Link Unit I/O Refresh Special I/O Unit Refresh Group-2 High-density I/O Unit Refresh 6-2 Calculating Cycle Time 6-2-1 PC with I/O Units Only 6-2-2 PC with Host Link and Remote I/O Master Units Page 6-3 Instruction Execution Times Page Page Page Page Page Page Page Page 6-4 I/O Response Time 6-4-1 Basic Systems 6-4-2 Remote I/O Systems Page Page 6-4-3 Host Link Systems 6-4-4 PC Link Systems Page Page 6-4-5 One-to-one Link I/O Response Time Page 6-4-6 Interrupt Response Times Page Page SECTION 7 Program Monitoring and Execution 7-1 Monitoring Operation and Modifying Data 7-2 Programming Console Operations 7-2-1 Bit/Word Monitor Page Page 7-2-2 Forced Set/Reset Page 7-2-3 Forced Set/Reset Cancel 7-2-4 Hexadecimal/BCD Data Modification Page 7-2-5 Hex/ASCII Display Change 7-2-6 4-digit Hex/Decimal Display Change 7-2-7 8-digit Hex/Decimal Display Change 7-2-8 Differentiation Monitor 7-2-9 3-word Monitor 7-2-10 3-word Data Modification 7-2-11 Binary Monitor Page 7-2-12 Binary Data Modification 7-2-13 Changing Timer/Counter SV Page Page 7-2-14 Expansion Instruction Function Code Assignments 7-2-15 UM Area Allocation 7-2-16 Reading and Setting the Clock 7-2-17 Expansion Keyboard Mapping 7-2-18 Keyboard Mapping Page Page Page SECTION 8 Serial Communications 418 Introduction Section 8-1 8-1 Introduction 8-2 Host Link Communications 8-2-1 Host Link Command Summary Page Page 8-2-2 Host Link Communications Page Page 8-2-3 Example Programs 8-3 RS-232C Communications 8-3-1 Communications Frame Structure 8-3-2 Communications Procedure Page 8-3-3 Application Example 430 One-to-one PC Links Section 8-4 8-4 One-to-one PC Links 431 One-to-one PC Links Section 8-4 432 NT Links Section 8-5 8-5 NT Links 8-6 The Protocol Macro Function 8-6-1 Introduction Page Page 8-6-2 Communications Board Settings 8-6-3 Communications Procedure Communications Sequence Structure The transmission message and reception message have the following struc- ture. Transmission/Reception Message Structure Page 8-6-4 Application Example Page Page 444 Reading and Clearing Errors and Messages Section 9-3 9-1 Alarm Indicators WARNING 9-2 Programmed Alarms and Error Messages 9-3 Reading and Clearing Errors and Messages 9-4 Error Messages 446 SYS FAIL FAL8B REMOTE ERR I/O VER ERR CYCLE TIME OVER 447 SIOU ERR * NO END INST MEMORY ERR - - - - - - - - - - - - - - - - - - - - 449 Error Flags Section 9-5 9-5 Error Flags 450 Host Link Errors Section 9-6 AR Area 9-6 Host Link Errors 451 Host Link Errors Section 9-6 SECTION 10 Host Link Commands 454 Host Link Command Summary Section 10-1 10-1 Host Link Command Summary 10-2 Host Link End Codes 10-2-1 End Code Summary Page 10-2-2 Command/End Code Table The following table shows which end codes can be returned for each command. 10-3 Host Link Commands 10-3-1 IR/SR AREA READ RR 10-3-2 LR AREA READ RL 10-3-3 HR AREA READ RH 10-3-4 PV READ RC 10-3-5 TC STATUS READ RG 10-3-6 DM AREA READ RD 10-3-7 AR AREA READ RJ Reads the contents of the specified number of AR words, starting from the speci- fied word. Limitations The text portion of the responses first frame can contain up to 30 words. PC Mode UM Area RUN MONITOR PROGRAM Write-protected Read-protected OK OK OK OK OK Commands Responses Single Multiple Single Multiple OK --- OK --- 10-3-9 IR/SR AREA WRITE WR 10-3-10 LR AREA WRITE WL 10-3-11 HR AREA WRITE WH 10-3-12 PV WRITE WC 10-3-13 TC STATUS WRITE WG 10-3-14 DM AREA WRITE WD 10-3-15 AR AREA WRITE WJ 10-3-16 EM AREA WRITE WE 10-3-17 SV READ 1 R# 10-3-18 SV READ 2 R$ Page 10-3-19 SV READ 3 R% 10-3-20 SV CHANGE 1 W# 10-3-21 SV CHANGE 2 W$ Page 10-3-22 SV CHANGE 3 W% 10-3-23 STATUS READ MS 00 1 000 PC Mode UM Area RUN MONITOR PROGRAM Write-protected Read-protected OK OK OK OK OK Commands Responses Single Multiple Single Multiple OK --- OK --- End code Contents 00 Normal completion 13 FCS error 14 Format error 18 Frame length error 10-3-24 STATUS WRITE SC Changes the PC operating mode. 000000 10-3-25 ERROR READ MF Reads and clears errors in the PC. Also checks whether previous errors have been cleared. 000 00 10-3-26 FORCED SET KS 10-3-27 FORCED RESET KR Page 10-3-28 MULTIPLE FORCED SET/RESET FK 10-3-29 FORCED SET/RESET CANCEL KC 10-3-30 PC MODEL READ MM Model code indicates the PC model in two digits hexadecimal. 10-3-31 TEST TS 10-3-32 PROGRAM READ RP 10-3-33 PROGRAM WRITE WP 10-3-34 I/O TABLE GENERATE MI Corrects the registered I/O table to match the actual I/O table. Note The write-protected error code for this command is different from the other com- mands. 10-3-35 COMPOUND COMMAND QQMR 10-3-36 COMPOUND COMMAND DATA READ QQIR 10-3-37 ABORT XZ 10-3-38 INITIALIZE 10-3-39 TXD RESPONSE EX 10-3-40 Undefined Command IC Appendix A Standard Models CPU Rack Expansion I/O Racks Slave Racks I/O Units Group-2 I/O Units Special I/O Units Page Communication Units SYSMAC NET/SYSMAC LINK Hardware Link Adapters Optical Fiber Products Optical Fiber Cable for SYSMAC NET and SYSMAC LINK H-PCF Optical Fiber Cable with Connectors S3200-CN-20-25 Plastic Clad Optical Fiber Cable for SYSMAC BUS H-PCF Optical Fiber Cables (For SYSMAC NET, SYSMAC LINK, and SYSMAC BUS) Page Optical Power Tester Programming Devices Optional Products Mounting Rails and Accessories Note: Order DIN Tracks, End Plates, and Spacers in units of 10 each. SYSMAC Support Software (SSS) Protocol Support Software Training Materials Appendix B Programming Instructions Page Page Expansion Instructions Page Page Appendix C Error and Arithmetic Flag Operation Expansion Instructions The default function codes are shown for the instructions that have default function codes. Page Page Page 528 I/O Bits 529 Work Bits Page Page Page Page Appendix F Data Conversion Tables Normal Data Standard Models Appendix F 536 Signed Binary Data Appendix G Extended ASCII Programming Console Displays Glossary Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Index A B C D E F G-H I J-L using KEEP(11), 121 using OUT and OUT NOT, 150 M N-O P R S T U-W 561 Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W303-E1-4 Revision code Date Revised content 1June 1996 Original production 2 January 1998 3January 2000 Page xiv: Safety precautions rearranged and reworded.