Philips ISP1520 9. Conguration selections

Philips Semiconductors ISP1520

Hi-Speed USB hub controller

Product data Rev. 03 — 24 November 2004 12 of 51

9397 750 13701 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

9. Conﬁguration selections

The ISP1520 is conﬁgured through I/O pins and, optionally, through an external

I2C-bus, in which case the hub can update its conﬁgurationdescr iptors as a master or

as a slave.

Tab le 3 shows the conﬁguration parameters.

[1] Multiple ganged power mode is reported as individual power mode; refer to the USB 2.0 speciﬁcation.

[2] When the hub uses the global overcurrent protection mode, the overcurrentindication is through the wHubStatus ﬁeld bit 1 (overcurrent)

and the corresponding change bit (overcurrent change).

9.1 Conﬁguration through I/O pins

9.1.1 Number of downstream facing ports

To discount a physical downstream facing port, connect pins DP and DM of that

downstream facing port to VCC (3.3 V) starting from the highest port number (4).

The sum of physical ports conﬁgured is reﬂected in the bNbrPorts ﬁeld.

Table 3: Conﬁguration parameters

Mode and selection Option Conﬁguration method

Pin control Software control

Control pin Reference Affected ﬁeld Reference

Numberof downstream

facing ports 2 por ts

3 ports

4 ports

DM1/DP1 to

DM4/DP4 see Section 9.1.1 bNbrPorts0 see Tabl e 22

Power switching mode ganged

multiple ganged[1]

individual

PSW1_N to

PSW4_N see Section 9.1.2 wHubCharacteristics:

bits D1 and D0 see Ta ble 22

bPwrOn2PwrGood:

time interval

Overcurrent protection

mode none

global[2]

multiple ganged

individual

NOOC and

OC1_N to

OC4_N

see Section 9.1.3 wHubCharacteristics:

bits D4 and D3 see Ta ble 22

Non-removable ports any port can be

non-removable AMBn_N see Section 9.1.4 wHubCharacteristics:

bit D2 (compound hub) see Tabl e 22

DeviceRemovable:

bit map

Port indicator support no

yes all GRNn_N see Section 9.1.5 wHubCharacteristics:

bit D7 see Tabl e 22

Table 4: Downstream facing port number pin conﬁguration

Number of physical

downstream facing port DM1/DP1 DM2/DP2 DM3/DP3 DM4/DP4

415kΩ

pull-down 15 kΩ

pull-down 15 kΩ

pull-down 15 kΩ

pull-down

315kΩ

pull-down 15 kΩ

pull-down 15 kΩ

pull-down VCC

215kΩ

pull-down 15 kΩ

pull-down VCC VCC

Contents

Main ISP1520 Hi-Speed Universal Serial Bus hub controller Universal Serial Bus Specication Rev.2.0 Rev. 03 24 November 2004 Product data 1. General description 2. Features Universal Serial Bus Specication Rev.2.0 3. Applications 4. Abbreviations 5. Ordering information Product data Rev. 03 24 November 2004 4 of 51 6. Block diagram Fig 1. Block diagram. ISP1520 Philips Semiconductors ISP1520 Product data Rev. 03 24 November 2004 5 of 51 7. Pinning information ISP1520BD Fig 2. Pin conguration. 7.2 Pin description 7.1 Pinning Page ISP1520 Hub Demo Board Users Guide Page 8. Functional description 8.3 Phase-locked loop clock multiplier 8.4 I2C-bus controller 8.5 Overcurrent detection circuit 8.6 GoodLink 8.7 Power-on reset Fig 4. External clock with respect to power-on reset. Fig 3. Power-on reset timing. Stable external clock is to be available at A. POR EXTERNAL CLOCK A 9. Conguration selections 9.1 Conguration through I/O pins Page Philips Semiconductors ISP1520 9.2 Device descriptors and string descriptors settings using I2C-bus The I C-bus specication Page 9.2.3 ROM or EEPROM map Page Page Philips Semiconductors ISP1520 Page 10. Hub controller description 11. Descriptors Page Page 12. Hub requests Tab le 23 shows the suppor ted standard USB requests. 12.1 Standard USB requests 12.2 Hub class requests Tab le 24 shows the hub class requests. 12.3 Detailed responses to hub requests Page Page 12.4 Various get descriptors bmRequestType 10000000B bmRequest GET_DESCRIPTOR = 6 13. Limiting values 14. Recommended operating conditions In accordance with the Absolute Maximum Rating System (IEC 60134). 15. Static characteristics Page Page 16. Dynamic characteristics C; test circuit Figure 21; unless otherwise specied. Page TPERIOD is the bit duration corresponding with the USB data rate. Fig 11. Source differential data-to-EOP transition skew and EOP width. TPERIOD is the bit duration corresponding with the USB data rate. tJR is the jitter reference point. Fig 13. Receiver SE0 width tolerance. Fig 12. Receiver differential data jitter. Fig 14. Hub differential data delay and SOP distortion. Fig 15. Hub EOP delay and EOP skew. and T within recommended operating range; V 5 V; V =V ; V 17. Application information 17.1 Descriptor conguration selection ISP1520 Fig 18. Adjusting analog overcurrent detection limit (optional). ISP1520 17.3 Self-powered hub congurations ISP1520 Fig 19. Self-powered hub; individual port power switching; individual overcurrent detection. Fig 20. Self-powered hub; ganged port power switching; global overcurrent detection. ISP1520 18. Test information DMn D Fig 22. Full-speed test circuit. Fig 21. High-speed transmitter and receiver test circuit. 19. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 Fig 23. LQFP64 package outline. c 20. Soldering 20.1 Introduction to soldering surface mount packages Data Handbook IC26; Integrated Circuit Packages 20.2 Reow soldering 20.3 Wave soldering 21. Revision history Contact information 22. Data sheet status 23. Denitions 24. Disclaimers 25. Licenses 26. Trademarks Contents