Philips ISP1520 8. Functional description

Philips Semiconductors ISP1520

Hi-Speed USB hub controller

Product data Rev. 03 — 24 November 2004 9 of 51

9397 750 13701 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.

8. Functional description

8.1 Analog transceivers

The integrated transceivers directly interface to USB lines. They can transmit and

receive serial data at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed

(1.5 Mbit/s).

8.2 Hub controller core

The main components of the hub core are:

•Philips Serial Interface Engine (SIE)

•Routing logic

•Transaction Translator (TT)

•Mini-host controller

•Hub repeater

•Hub controller

•Port controller

•Bit clock recovery.

8.2.1 Philips serial interface engine

The Philips SIE implements the full USB protocol layer. It is completely hardwired for

speed and needs no ﬁrmware intervention. The functions of this block include:

synchronization, pattern recognition, parallel or serial conversion, bit (de-)stufﬁng,

CRC checking and generation, Packet IDentiﬁer veriﬁcation and generation, address

recognition, and handshake evaluation and generation.

8.2.2 Routing logic

The routing logic directs signaling to the appropriate modules (mini-host controller,

Original USB repeater and Hi-Speed USB repeater) according to the topology in

which the hub is placed.

8.2.3 Transaction translator

The TT acts as a go-between mechanism that links devices operating in the Original

USB mode and the Hi-Speed USB upstream mode. For the ‘IN’ direction, data is

concatenated in TT buffers till the proper length is reached, beforethe host takes the

transaction. In the reverse direction (OUT), the mini-host dispenses the data

contained in TT buffers over a period that ﬁts into the Original USB bandwidth. This

continues until all outgoing data is emptied. TT buffers are used only on split

transactions.

8.2.4 Mini-host controller

The internal mini-host generates all the Original USB IN, OUT or SETUP tokens for

the downstream facing ports, while the upstream facing port is in the high-speed

mode. The responses from the Original USB devices are collected in TT buffers,until

the end of the complete split transaction clears the TT buffers.

Contents

Main ISP1520 Hi-Speed Universal Serial Bus hub controller Universal Serial Bus Specication Rev.2.0 Rev. 03 24 November 2004 Product data 1. General description 2. Features Universal Serial Bus Specication Rev.2.0 3. Applications 4. Abbreviations 5. Ordering information Product data Rev. 03 24 November 2004 4 of 51 6. Block diagram Fig 1. Block diagram. ISP1520 Philips Semiconductors ISP1520 Product data Rev. 03 24 November 2004 5 of 51 7. Pinning information ISP1520BD Fig 2. Pin conguration. 7.2 Pin description 7.1 Pinning Page ISP1520 Hub Demo Board Users Guide Page 8. Functional description 8.3 Phase-locked loop clock multiplier 8.4 I2C-bus controller 8.5 Overcurrent detection circuit 8.6 GoodLink 8.7 Power-on reset Fig 4. External clock with respect to power-on reset. Fig 3. Power-on reset timing. Stable external clock is to be available at A. POR EXTERNAL CLOCK A 9. Conguration selections 9.1 Conguration through I/O pins Page Philips Semiconductors ISP1520 9.2 Device descriptors and string descriptors settings using I2C-bus The I C-bus specication Page 9.2.3 ROM or EEPROM map Page Page Philips Semiconductors ISP1520 Page 10. Hub controller description 11. Descriptors Page Page 12. Hub requests Tab le 23 shows the suppor ted standard USB requests. 12.1 Standard USB requests 12.2 Hub class requests Tab le 24 shows the hub class requests. 12.3 Detailed responses to hub requests Page Page 12.4 Various get descriptors bmRequestType 10000000B bmRequest GET_DESCRIPTOR = 6 13. Limiting values 14. Recommended operating conditions In accordance with the Absolute Maximum Rating System (IEC 60134). 15. Static characteristics Page Page 16. Dynamic characteristics C; test circuit Figure 21; unless otherwise specied. Page TPERIOD is the bit duration corresponding with the USB data rate. Fig 11. Source differential data-to-EOP transition skew and EOP width. TPERIOD is the bit duration corresponding with the USB data rate. tJR is the jitter reference point. Fig 13. Receiver SE0 width tolerance. Fig 12. Receiver differential data jitter. Fig 14. Hub differential data delay and SOP distortion. Fig 15. Hub EOP delay and EOP skew. and T within recommended operating range; V 5 V; V =V ; V 17. Application information 17.1 Descriptor conguration selection ISP1520 Fig 18. Adjusting analog overcurrent detection limit (optional). ISP1520 17.3 Self-powered hub congurations ISP1520 Fig 19. Self-powered hub; individual port power switching; individual overcurrent detection. Fig 20. Self-powered hub; ganged port power switching; global overcurrent detection. ISP1520 18. Test information DMn D Fig 22. Full-speed test circuit. Fig 21. High-speed transmitter and receiver test circuit. 19. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 Fig 23. LQFP64 package outline. c 20. Soldering 20.1 Introduction to soldering surface mount packages Data Handbook IC26; Integrated Circuit Packages 20.2 Reow soldering 20.3 Wave soldering 21. Revision history Contact information 22. Data sheet status 23. Denitions 24. Disclaimers 25. Licenses 26. Trademarks Contents