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Philips TDA9964 Fig 9. Serial interface block diagram., Fig 10. Loading sequence of control input data via the serial interface.

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Philips Semiconductors TDA9964

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Objective speciﬁcation Rev. 03 — 16 January 2001 13 of 23

Fig 9. Serial interface block diagram.

OFDOUT DAC

LATCHES PGA GAIN

LATCHES ADC CLAMP

LATCHES

CONTROL PULSE

POLARITY

LATCHES

LATCH

SELECTION

SD0

LSB MSB

SDATA

SCLK

SEN

SCLK

8-bit DAC

FCE523

PGA control ADC clamp

control control pulses

polarity settings

SD2SD1 SD3 SD4 SD5

SD6

SHIFT REGISTER

SD7 SD8 SD9 SD10 SD11

8 8 7 10

A0 A1 A2 A3

VSYNC

FLIP-FLOP FLIP-FLOP FLIP-FLOP

tsu1=t

su2=t

su3= 10ns (min.); thd3 =t

hd4= 10ns (min.)

Fig 10. Loading sequence of control input data via the serial interface.

FCE524

SDATA

SCLK

SEN

SD11

A1A2

A3 A0 SD9

SD10 SD7 SD6 SD5 SD4 SD3

MSB LSB

SD2 SD1 SD0

thd3

tsu3

tsu1

thd4

tsu2

SD8

Contents

Main TDA9964 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Rev. 03 16 January 2001 Objective specication 1. Description 2. Features 4. Quick reference data 5. Ordering information 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Objective specication Rev. 03 16 January 2001 3 of 23 hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh 6. Block diagram Fig 1. Block diagram. TDA9964 Philips Semiconductors TDA9964 7. Pinning information Fig 2. Pin conguration. 7.2 Pin description 7.1 Pinning TDA9964HL Page Philips Semiconductors TDA9964 8. Limiting values 9. Thermal characteristics 10. Characteristics In accordance with the Absolute Maximum Rating System (IEC 60134). = 3.0V; V = 2.7V; f = 3.0 V; V = 2.7 V; f = 30 MHz; T = 3.0 V; V = 2.7 V; f = 30 MHz; T Philips Semiconductors TDA9964 Fig 3. Pixel frequency timing diagram; all polarities active HIGH. Fig 4. Pixel frequency timing diagram; all polarities active LOW. Fig 5. DAC voltage output as a function of DAC input code. Fig 6. Line frequency timing diagram. 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Fig 7. Total gain from CDS input to ADC input as a function of PGA input code. Fig 8. Typical total noise performance as a function of PGA gain. Fig 9. Serial interface block diagram. VSYNC Fig 10. Loading sequence of control input data via the serial interface. tsu1=t Page 11. Application information D1 D0 TDA9964 Fig 11. Application diagram. 11.1 Power and grounding recommendations 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 Fig 12. SOT313-2. 13. Handling information 14. Soldering 14.1 Introduction to soldering surface mount packages Data Handbook IC26; Integrated Circuit Packages 14.2 Reow soldering 15. Revision history 16. Data sheet status 17. Denitions 18. Disclaimers Philips Semiconductors - a worldwide company Internet: http://www.semiconductors.philips.com Contents